From c1bc0edc79cccc2d19eca8d44e43fa5a5962628b Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Sat, 21 Nov 2020 17:51:28 +0800 Subject: [PATCH] [mips][wasm][memory64] Prepare Liftoff for ptrsize offsets Port: commit 1da429fb8a9c1fa37400256b67f12fa4bb95d372 Bug: v8:10949 Change-Id: I77d28b26a78fe098b529d6ac333c0dac49850b4f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2553160 Reviewed-by: Zhao Jiazhong Reviewed-by: Clemens Backes Commit-Queue: Clemens Backes Auto-Submit: Liu yu Cr-Commit-Position: refs/heads/master@{#71331} --- .../baseline/mips/liftoff-assembler-mips.h | 12 ++++-- .../mips64/liftoff-assembler-mips64.h | 41 +++++++++++-------- 2 files changed, 32 insertions(+), 21 deletions(-) diff --git a/src/wasm/baseline/mips/liftoff-assembler-mips.h b/src/wasm/baseline/mips/liftoff-assembler-mips.h index 5c78eca319..7762b389a4 100644 --- a/src/wasm/baseline/mips/liftoff-assembler-mips.h +++ b/src/wasm/baseline/mips/liftoff-assembler-mips.h @@ -861,9 +861,15 @@ I32_SHIFTOP_I(shr, srl) #undef I32_SHIFTOP_I void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs, - int32_t imm) { + int64_t imm) { + LiftoffRegister imm_reg = + GetUnusedRegister(kFpReg, LiftoffRegList::ForRegs(dst, lhs)); + int32_t imm_low_word = static_cast(imm); + int32_t imm_high_word = static_cast(imm >> 32); + TurboAssembler::li(imm_reg.low_gp(), imm_low_word); + TurboAssembler::li(imm_reg.high_gp(), imm_high_word); TurboAssembler::AddPair(dst.low_gp(), dst.high_gp(), lhs.low_gp(), - lhs.high_gp(), imm, + lhs.high_gp(), imm_reg.low_gp(), imm_reg.high_gp(), kScratchReg, kScratchReg2); } @@ -1608,7 +1614,7 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, } void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr, - Register offset_reg, uint32_t offset_imm, + Register offset_reg, uintptr_t offset_imm, LoadType type, LoadTransformationKind transform, uint32_t* protected_load_pc) { diff --git a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h index aefc26bcb1..c355a3199a 100644 --- a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h +++ b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h @@ -49,11 +49,12 @@ inline MemOperand GetStackSlot(int offset) { return MemOperand(fp, -offset); } inline MemOperand GetInstanceOperand() { return GetStackSlot(kInstanceOffset); } inline MemOperand GetMemOp(LiftoffAssembler* assm, Register addr, - Register offset, uint32_t offset_imm) { + Register offset, uintptr_t offset_imm) { if (is_uint31(offset_imm)) { - if (offset == no_reg) return MemOperand(addr, offset_imm); + int32_t offset_imm32 = static_cast(offset_imm); + if (offset == no_reg) return MemOperand(addr, offset_imm32); assm->daddu(kScratchReg, addr, offset); - return MemOperand(kScratchReg, offset_imm); + return MemOperand(kScratchReg, offset_imm32); } // Offset immediate does not fit in 31 bits. assm->li(kScratchReg, offset_imm); @@ -404,7 +405,7 @@ void LiftoffAssembler::StoreTaggedPointer(Register dst_addr, } void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, - Register offset_reg, uint32_t offset_imm, + Register offset_reg, uintptr_t offset_imm, LoadType type, LiftoffRegList pinned, uint32_t* protected_load_pc, bool is_load_mem) { MemOperand src_op = liftoff::GetMemOp(this, src_addr, offset_reg, offset_imm); @@ -459,7 +460,7 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, } void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister src, + uintptr_t offset_imm, LiftoffRegister src, StoreType type, LiftoffRegList pinned, uint32_t* protected_store_pc, bool is_store_mem) { MemOperand dst_op = liftoff::GetMemOp(this, dst_addr, offset_reg, offset_imm); @@ -509,56 +510,56 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, } void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr, - Register offset_reg, uint32_t offset_imm, + Register offset_reg, uintptr_t offset_imm, LoadType type, LiftoffRegList pinned) { bailout(kAtomics, "AtomicLoad"); } void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister src, + uintptr_t offset_imm, LiftoffRegister src, StoreType type, LiftoffRegList pinned) { bailout(kAtomics, "AtomicStore"); } void LiftoffAssembler::AtomicAdd(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister value, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicAdd"); } void LiftoffAssembler::AtomicSub(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister value, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicSub"); } void LiftoffAssembler::AtomicAnd(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister value, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicAnd"); } void LiftoffAssembler::AtomicOr(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister value, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicOr"); } void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg, - uint32_t offset_imm, LiftoffRegister value, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicXor"); } void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg, - uint32_t offset_imm, + uintptr_t offset_imm, LiftoffRegister value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicExchange"); } void LiftoffAssembler::AtomicCompareExchange( - Register dst_addr, Register offset_reg, uint32_t offset_imm, + Register dst_addr, Register offset_reg, uintptr_t offset_imm, LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result, StoreType type) { bailout(kAtomics, "AtomicCompareExchange"); @@ -837,6 +838,11 @@ I32_SHIFTOP_I(shr, srl) #undef I32_SHIFTOP #undef I32_SHIFTOP_I +void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs, + int64_t imm) { + TurboAssembler::Daddu(dst.gp(), lhs.gp(), Operand(imm)); +} + void LiftoffAssembler::emit_i64_mul(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { TurboAssembler::Dmul(dst.gp(), lhs.gp(), rhs.gp()); @@ -909,7 +915,6 @@ I64_BINOP(xor, xor_) } // clang-format off -I64_BINOP_I(add, Daddu) I64_BINOP_I(and, And) I64_BINOP_I(or, Or) I64_BINOP_I(xor, Xor) @@ -1470,14 +1475,14 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, } void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr, - Register offset_reg, uint32_t offset_imm, + Register offset_reg, uintptr_t offset_imm, LoadType type, LoadTransformationKind transform, uint32_t* protected_load_pc) { UseScratchRegisterScope temps(this); Register scratch = temps.Acquire(); - Daddu(scratch, src_addr, offset_reg); - MemOperand src_op = MemOperand(scratch, offset_imm); + MemOperand src_op = + liftoff::GetMemOp(this, src_addr, offset_reg, offset_imm); MSARegister dst_msa = dst.fp().toW(); *protected_load_pc = pc_offset(); MachineType memtype = type.mem_type();