MIPS: ARM: Fix erroneous detection of Double result type in Integer32 BinaryOpStubs
Port r14371 (b5c4a990) BUG= Review URL: https://codereview.chromium.org/13973013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14384 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -2511,12 +2511,17 @@ void BinaryOpStub::GenerateInt32Stub(MacroAssembler* masm) {
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__ Addu(scratch2, scratch1, Operand(0x40000000));
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// If not try to return a heap number.
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__ Branch(&return_heap_number, lt, scratch2, Operand(zero_reg));
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// Check for minus zero. Return heap number for minus zero.
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// Check for minus zero. Return heap number for minus zero if
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// double results are allowed; otherwise transition.
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Label not_zero;
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__ Branch(¬_zero, ne, scratch1, Operand(zero_reg));
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__ mfc1(scratch2, f11);
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__ And(scratch2, scratch2, HeapNumber::kSignMask);
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__ Branch(&return_heap_number, ne, scratch2, Operand(zero_reg));
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__ Branch(result_type_ <= BinaryOpIC::INT32 ? &transition
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: &return_heap_number,
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ne,
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scratch2,
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Operand(zero_reg));
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__ bind(¬_zero);
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// Tag the result and return.
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@ -2529,21 +2534,18 @@ void BinaryOpStub::GenerateInt32Stub(MacroAssembler* masm) {
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__ bind(&return_heap_number);
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// Return a heap number, or fall through to type transition or runtime
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// call if we can't.
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if (result_type_ >= ((op_ == Token::DIV) ? BinaryOpIC::NUMBER
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: BinaryOpIC::INT32)) {
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// We are using FPU registers so s0 is available.
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heap_number_result = s0;
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BinaryOpStub_GenerateHeapResultAllocation(masm,
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heap_number_result,
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heap_number_map,
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scratch1,
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scratch2,
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&call_runtime,
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mode_);
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__ mov(v0, heap_number_result);
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__ sdc1(f10, FieldMemOperand(v0, HeapNumber::kValueOffset));
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__ Ret();
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}
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// We are using FPU registers so s0 is available.
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heap_number_result = s0;
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BinaryOpStub_GenerateHeapResultAllocation(masm,
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heap_number_result,
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heap_number_map,
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scratch1,
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scratch2,
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&call_runtime,
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mode_);
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__ mov(v0, heap_number_result);
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__ sdc1(f10, FieldMemOperand(v0, HeapNumber::kValueOffset));
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__ Ret();
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// A DIV operation expecting an integer result falls through
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// to type transition.
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