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MIPS: Fix simulator divide for overflow case.

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TEST=mjsunit/div-mul-minus-one.js
BUG=
R=gergely@homejinni.com

Review URL: https://codereview.chromium.org/24956002

Patch from Paul Lind <plind44@gmail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16982 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
palfia@homejinni.com 2013-09-27 10:42:51 +00:00
parent 936802ae21
commit c34af4ae6d
1 changed files with 7 additions and 3 deletions
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10
src/mips/simulator-mips.cc
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@ -2274,9 +2274,13 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
break;
case DIV:
// Divide by zero and overflow was not checked in the configuration
// step - div and divu do not raise exceptions. On division by 0 and
// on overflow (INT_MIN/-1), the result will be UNPREDICTABLE.
if (rt != 0 && !(rs == INT_MIN && rt == -1)) {
// step - div and divu do not raise exceptions. On division by 0
// the result will be UNPREDICTABLE. On overflow (INT_MIN/-1),
// return INT_MIN which is what the hardware does.
if (rs == INT_MIN && rt == -1) {
set_register(LO, INT_MIN);
set_register(HI, 0);
} else if (rt != 0) {
set_register(LO, rs / rt);
set_register(HI, rs % rt);
}