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[Turbofan] Add other integer SIMD types, add more integer ops.

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- Adds Int16x8, Int8x16 types.
- Adds neg, abs unary ops.
- Adds add, sub, mul, and signed / unsigned min / max, comparison ops.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2638133002
Cr-Commit-Position: refs/heads/master@{#42674}
This commit is contained in:
bbudge 2017-01-25 18:18:00 -08:00 committed by Commit bot
parent d28c04486b
commit c5bdbbbebe
16 changed files with 1536 additions and 88 deletions
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194
src/compiler/arm/code-generator-arm.cc
View File

@ -1578,6 +1578,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmInt32x4Neg: {
__ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmInt32x4Add: {
__ vadd(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
@ -1588,6 +1592,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kArmInt32x4Mul: {
__ vmul(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt32x4Min: {
__ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt32x4Max: {
__ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt32x4Eq: {
__ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
@ -1600,6 +1619,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vmvn(dst, dst);
break;
}
case kArmInt32x4Gt: {
__ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt32x4Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint32x4Gt: {
__ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint32x4Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmSimd32x4Select: {
// Select is a ternary op, so we need to move one input into the
// destination. Use vtst to canonicalize the 'boolean' input #0.
@ -1609,6 +1650,159 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(2));
break;
}
case kArmInt16x8Splat: {
__ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0));
break;
}
case kArmInt16x8ExtractLane: {
__ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS16,
i.InputInt8(1));
break;
}
case kArmInt16x8ReplaceLane: {
__ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputRegister(2), NeonS16, i.InputInt8(1));
break;
}
case kArmInt16x8Neg: {
__ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmInt16x8Add: {
__ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Sub: {
__ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Mul: {
__ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Min: {
__ vmin(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Max: {
__ vmax(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Eq: {
__ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Ne: {
Simd128Register dst = i.OutputSimd128Register();
__ vceq(Neon16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vmvn(dst, dst);
break;
}
case kArmInt16x8Gt: {
__ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt16x8Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint16x8Gt: {
__ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint16x8Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Splat: {
__ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0));
break;
}
case kArmInt8x16ExtractLane: {
__ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS8,
i.InputInt8(1));
break;
}
case kArmInt8x16ReplaceLane: {
__ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputRegister(2), NeonS8, i.InputInt8(1));
break;
}
case kArmInt8x16Neg: {
__ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kArmInt8x16Add: {
__ vadd(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Sub: {
__ vsub(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Mul: {
__ vmul(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Min: {
__ vmin(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Max: {
__ vmax(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Eq: {
__ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Ne: {
Simd128Register dst = i.OutputSimd128Register();
__ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
__ vmvn(dst, dst);
break;
}
case kArmInt8x16Gt: {
__ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmInt8x16Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS8, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint8x16Gt: {
__ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmUint8x16Ge: {
Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU8, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kCheckedLoadInt8:
ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb);
break;

40
src/compiler/arm/instruction-codes-arm.h
View File

@ -136,11 +136,49 @@ namespace compiler {
V(ArmInt32x4ReplaceLane) \
V(ArmInt32x4FromFloat32x4) \
V(ArmUint32x4FromFloat32x4) \
V(ArmInt32x4Neg) \
V(ArmInt32x4Add) \
V(ArmInt32x4Sub) \
V(ArmInt32x4Mul) \
V(ArmInt32x4Min) \
V(ArmInt32x4Max) \
V(ArmInt32x4Eq) \
V(ArmInt32x4Ne) \
V(ArmSimd32x4Select)
V(ArmInt32x4Gt) \
V(ArmInt32x4Ge) \
V(ArmUint32x4Gt) \
V(ArmUint32x4Ge) \
V(ArmSimd32x4Select) \
V(ArmInt16x8Splat) \
V(ArmInt16x8ExtractLane) \
V(ArmInt16x8ReplaceLane) \
V(ArmInt16x8Neg) \
V(ArmInt16x8Add) \
V(ArmInt16x8Sub) \
V(ArmInt16x8Mul) \
V(ArmInt16x8Min) \
V(ArmInt16x8Max) \
V(ArmInt16x8Eq) \
V(ArmInt16x8Ne) \
V(ArmInt16x8Gt) \
V(ArmInt16x8Ge) \
V(ArmUint16x8Gt) \
V(ArmUint16x8Ge) \
V(ArmInt8x16Splat) \
V(ArmInt8x16ExtractLane) \
V(ArmInt8x16ReplaceLane) \
V(ArmInt8x16Neg) \
V(ArmInt8x16Add) \
V(ArmInt8x16Sub) \
V(ArmInt8x16Mul) \
V(ArmInt8x16Min) \
V(ArmInt8x16Max) \
V(ArmInt8x16Eq) \
V(ArmInt8x16Ne) \
V(ArmInt8x16Gt) \
V(ArmInt8x16Ge) \
V(ArmUint8x16Gt) \
V(ArmUint8x16Ge)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes

38
src/compiler/arm/instruction-scheduler-arm.cc
View File

@ -124,11 +124,49 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmInt32x4ReplaceLane:
case kArmInt32x4FromFloat32x4:
case kArmUint32x4FromFloat32x4:
case kArmInt32x4Neg:
case kArmInt32x4Add:
case kArmInt32x4Sub:
case kArmInt32x4Mul:
case kArmInt32x4Min:
case kArmInt32x4Max:
case kArmInt32x4Eq:
case kArmInt32x4Ne:
case kArmInt32x4Gt:
case kArmInt32x4Ge:
case kArmUint32x4Gt:
case kArmUint32x4Ge:
case kArmSimd32x4Select:
case kArmInt16x8Splat:
case kArmInt16x8ExtractLane:
case kArmInt16x8ReplaceLane:
case kArmInt16x8Neg:
case kArmInt16x8Add:
case kArmInt16x8Sub:
case kArmInt16x8Mul:
case kArmInt16x8Min:
case kArmInt16x8Max:
case kArmInt16x8Eq:
case kArmInt16x8Ne:
case kArmInt16x8Gt:
case kArmInt16x8Ge:
case kArmUint16x8Gt:
case kArmUint16x8Ge:
case kArmInt8x16Splat:
case kArmInt8x16ExtractLane:
case kArmInt8x16ReplaceLane:
case kArmInt8x16Neg:
case kArmInt8x16Add:
case kArmInt8x16Sub:
case kArmInt8x16Mul:
case kArmInt8x16Min:
case kArmInt8x16Max:
case kArmInt8x16Eq:
case kArmInt8x16Ne:
case kArmInt8x16Gt:
case kArmInt8x16Ge:
case kArmUint8x16Gt:
case kArmUint8x16Ge:
return kNoOpcodeFlags;
case kArmVldrF32:

233
src/compiler/arm/instruction-selector-arm.cc
View File

@ -2286,6 +2286,7 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
Emit(code, 0, nullptr, input_count, inputs);
}
// TODO(bbudge) Macro-ize SIMD methods.
void InstructionSelector::VisitCreateFloat32x4(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmFloat32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
@ -2386,6 +2387,12 @@ void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) {
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitInt32x4Neg(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Neg, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitInt32x4Add(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Add, g.DefineAsRegister(node),
@ -2398,6 +2405,24 @@ void InstructionSelector::VisitInt32x4Sub(Node* node) {
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4Mul(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Mul, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4Min(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Min, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4Max(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Max, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4Equal(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
@ -2410,6 +2435,30 @@ void InstructionSelector::VisitInt32x4NotEqual(Node* node) {
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt32x4GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt32x4Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint32x4GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint32x4Gt, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint32x4GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint32x4Ge, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitSimd32x4Select(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmSimd32x4Select, g.DefineAsRegister(node),
@ -2417,6 +2466,190 @@ void InstructionSelector::VisitSimd32x4Select(Node* node) {
g.UseRegister(node->InputAt(2)));
}
void InstructionSelector::VisitCreateInt16x8(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitInt16x8ExtractLane(Node* node) {
ArmOperandGenerator g(this);
int32_t lane = OpParameter<int32_t>(node);
Emit(kArmInt16x8ExtractLane, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
}
void InstructionSelector::VisitInt16x8ReplaceLane(Node* node) {
ArmOperandGenerator g(this);
int32_t lane = OpParameter<int32_t>(node);
Emit(kArmInt16x8ReplaceLane, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
g.Use(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Neg(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Neg, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitInt16x8Add(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Add, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Sub(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Sub, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Mul(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Mul, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Min(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Min, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Max(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Max, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8Equal(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8NotEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt16x8GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt16x8Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint16x8GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint16x8Gt, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint16x8GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint16x8Ge, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitCreateInt8x16(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitInt8x16ExtractLane(Node* node) {
ArmOperandGenerator g(this);
int32_t lane = OpParameter<int32_t>(node);
Emit(kArmInt8x16ExtractLane, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
}
void InstructionSelector::VisitInt8x16ReplaceLane(Node* node) {
ArmOperandGenerator g(this);
int32_t lane = OpParameter<int32_t>(node);
Emit(kArmInt8x16ReplaceLane, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
g.Use(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Neg(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Neg, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)));
}
void InstructionSelector::VisitInt8x16Add(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Add, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Sub(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Sub, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Mul(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Mul, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Min(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Min, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Max(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Max, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16Equal(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16NotEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitInt8x16GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmInt8x16Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint8x16GreaterThan(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint8x16Gt, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
void InstructionSelector::VisitUint8x16GreaterThanOrEqual(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmUint8x16Ge, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
}
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {

38
src/compiler/common-operator.cc
View File

@ -1353,44 +1353,6 @@ const Operator* CommonOperatorBuilder::ResizeMergeOrPhi(const Operator* op,
}
}
const Operator* CommonOperatorBuilder::Int32x4ExtractLane(int32_t lane_number) {
DCHECK(0 <= lane_number && lane_number < 4);
return new (zone()) Operator1<int32_t>( // --
IrOpcode::kInt32x4ExtractLane, Operator::kPure, // opcode
"Int32x4ExtractLane", // name
1, 0, 0, 1, 0, 0, // counts
lane_number); // parameter
}
const Operator* CommonOperatorBuilder::Int32x4ReplaceLane(int32_t lane_number) {
DCHECK(0 <= lane_number && lane_number < 4);
return new (zone()) Operator1<int32_t>( // --
IrOpcode::kInt32x4ReplaceLane, Operator::kPure, // opcode
"Int32x4ReplaceLane", // name
2, 0, 0, 1, 0, 0, // counts
lane_number); // parameter
}
const Operator* CommonOperatorBuilder::Float32x4ExtractLane(
int32_t lane_number) {
DCHECK(0 <= lane_number && lane_number < 4);
return new (zone()) Operator1<int32_t>( // --
IrOpcode::kFloat32x4ExtractLane, Operator::kPure, // opcode
"Float32x4ExtractLane", // name
1, 0, 0, 1, 0, 0, // counts
lane_number); // parameter
}
const Operator* CommonOperatorBuilder::Float32x4ReplaceLane(
int32_t lane_number) {
DCHECK(0 <= lane_number && lane_number < 4);
return new (zone()) Operator1<int32_t>( // --
IrOpcode::kFloat32x4ReplaceLane, Operator::kPure, // opcode
"Float32x4ReplaceLane", // name
2, 0, 0, 1, 0, 0, // counts
lane_number); // parameter
}
const FrameStateFunctionInfo*
CommonOperatorBuilder::CreateFrameStateFunctionInfo(
FrameStateType type, int parameter_count, int local_count,

6
src/compiler/common-operator.h
View File

@ -386,12 +386,6 @@ class V8_EXPORT_PRIVATE CommonOperatorBuilder final
// with {size} inputs.
const Operator* ResizeMergeOrPhi(const Operator* op, int size);
// Simd Operators
const Operator* Int32x4ExtractLane(int32_t);
const Operator* Int32x4ReplaceLane(int32_t);
const Operator* Float32x4ExtractLane(int32_t);
const Operator* Float32x4ReplaceLane(int32_t);
// Constructs function info for frame state construction.
const FrameStateFunctionInfo* CreateFrameStateFunctionInfo(
FrameStateType type, int parameter_count, int local_count,

53
src/compiler/graph.h
View File

@ -104,6 +104,59 @@ class V8_EXPORT_PRIVATE Graph final : public NON_EXPORTED_BASE(ZoneObject) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12, Node* n13) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12, Node* n13, Node* n14) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13, n14};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12, Node* n13, Node* n14, Node* n15) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, n14, n15};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12, Node* n13, Node* n14, Node* n15,
Node* n16) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, n14, n15, n16};
return NewNode(op, arraysize(nodes), nodes);
}
Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
Node* n11, Node* n12, Node* n13, Node* n14, Node* n15,
Node* n16, Node* n17) {
Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9,
n10, n11, n12, n13, n14, n15, n16, n17};
return NewNode(op, arraysize(nodes), nodes);
}
// Clone the {node}, and assign a new node id to the copy.
Node* CloneNode(const Node* node);

202
src/compiler/instruction-selector.cc
View File

@ -1482,16 +1482,92 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitInt32x4FromFloat32x4(node);
case IrOpcode::kUint32x4FromFloat32x4:
return MarkAsSimd128(node), VisitUint32x4FromFloat32x4(node);
case IrOpcode::kInt32x4Neg:
return MarkAsSimd128(node), VisitInt32x4Neg(node);
case IrOpcode::kInt32x4Add:
return MarkAsSimd128(node), VisitInt32x4Add(node);
case IrOpcode::kInt32x4Sub:
return MarkAsSimd128(node), VisitInt32x4Sub(node);
case IrOpcode::kInt32x4Mul:
return MarkAsSimd128(node), VisitInt32x4Mul(node);
case IrOpcode::kInt32x4Min:
return MarkAsSimd128(node), VisitInt32x4Min(node);
case IrOpcode::kInt32x4Max:
return MarkAsSimd128(node), VisitInt32x4Max(node);
case IrOpcode::kInt32x4Equal:
return MarkAsSimd128(node), VisitInt32x4Equal(node);
case IrOpcode::kInt32x4NotEqual:
return MarkAsSimd128(node), VisitInt32x4NotEqual(node);
case IrOpcode::kInt32x4GreaterThan:
return MarkAsSimd128(node), VisitInt32x4GreaterThan(node);
case IrOpcode::kInt32x4GreaterThanOrEqual:
return MarkAsSimd128(node), VisitInt32x4GreaterThanOrEqual(node);
case IrOpcode::kUint32x4GreaterThan:
return MarkAsSimd128(node), VisitUint32x4GreaterThan(node);
case IrOpcode::kUint32x4GreaterThanOrEqual:
return MarkAsSimd128(node), VisitUint32x4GreaterThanOrEqual(node);
case IrOpcode::kSimd32x4Select:
return MarkAsSimd128(node), VisitSimd32x4Select(node);
case IrOpcode::kCreateInt16x8:
return MarkAsSimd128(node), VisitCreateInt16x8(node);
case IrOpcode::kInt16x8ExtractLane:
return MarkAsWord32(node), VisitInt16x8ExtractLane(node);
case IrOpcode::kInt16x8ReplaceLane:
return MarkAsSimd128(node), VisitInt16x8ReplaceLane(node);
case IrOpcode::kInt16x8Neg:
return MarkAsSimd128(node), VisitInt16x8Neg(node);
case IrOpcode::kInt16x8Add:
return MarkAsSimd128(node), VisitInt16x8Add(node);
case IrOpcode::kInt16x8Sub:
return MarkAsSimd128(node), VisitInt16x8Sub(node);
case IrOpcode::kInt16x8Mul:
return MarkAsSimd128(node), VisitInt16x8Mul(node);
case IrOpcode::kInt16x8Min:
return MarkAsSimd128(node), VisitInt16x8Min(node);
case IrOpcode::kInt16x8Max:
return MarkAsSimd128(node), VisitInt16x8Max(node);
case IrOpcode::kInt16x8Equal:
return MarkAsSimd128(node), VisitInt16x8Equal(node);
case IrOpcode::kInt16x8NotEqual:
return MarkAsSimd128(node), VisitInt16x8NotEqual(node);
case IrOpcode::kInt16x8GreaterThan:
return MarkAsSimd128(node), VisitInt16x8GreaterThan(node);
case IrOpcode::kInt16x8GreaterThanOrEqual:
return MarkAsSimd128(node), VisitInt16x8GreaterThanOrEqual(node);
case IrOpcode::kUint16x8GreaterThan:
return MarkAsSimd128(node), VisitUint16x8GreaterThan(node);
case IrOpcode::kUint16x8GreaterThanOrEqual:
return MarkAsSimd128(node), VisitUint16x8GreaterThanOrEqual(node);
case IrOpcode::kCreateInt8x16:
return MarkAsSimd128(node), VisitCreateInt8x16(node);
case IrOpcode::kInt8x16ExtractLane:
return MarkAsWord32(node), VisitInt8x16ExtractLane(node);
case IrOpcode::kInt8x16ReplaceLane:
return MarkAsSimd128(node), VisitInt8x16ReplaceLane(node);
case IrOpcode::kInt8x16Neg:
return MarkAsSimd128(node), VisitInt8x16Neg(node);
case IrOpcode::kInt8x16Add:
return MarkAsSimd128(node), VisitInt8x16Add(node);
case IrOpcode::kInt8x16Sub:
return MarkAsSimd128(node), VisitInt8x16Sub(node);
case IrOpcode::kInt8x16Mul:
return MarkAsSimd128(node), VisitInt8x16Mul(node);
case IrOpcode::kInt8x16Min:
return MarkAsSimd128(node), VisitInt8x16Min(node);
case IrOpcode::kInt8x16Max:
return MarkAsSimd128(node), VisitInt8x16Max(node);
case IrOpcode::kInt8x16Equal:
return MarkAsSimd128(node), VisitInt8x16Equal(node);
case IrOpcode::kInt8x16NotEqual:
return MarkAsSimd128(node), VisitInt8x16NotEqual(node);
case IrOpcode::kInt8x16GreaterThan:
return MarkAsSimd128(node), VisitInt8x16GreaterThan(node);
case IrOpcode::kInt8x16GreaterThanOrEqual:
return MarkAsSimd128(node), VisitInt8x16GreaterThanOrEqual(node);
case IrOpcode::kUint8x16GreaterThan:
return MarkAsSimd128(node), VisitUint8x16GreaterThan(node);
case IrOpcode::kUint8x16GreaterThanOrEqual:
return MarkAsSimd128(node), VisitUint16x8GreaterThanOrEqual(node);
default:
V8_Fatal(__FILE__, __LINE__, "Unexpected operator #%d:%s @ node #%d",
node->opcode(), node->op()->mnemonic(), node->id());
@ -1876,11 +1952,137 @@ void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4Equal(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4NotEqual(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4LessThan(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32x4LessThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt32x4GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt32x4GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint32x4GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint32x4GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitSimd32x4Select(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitCreateInt16x8(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8ExtractLane(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt16x8ReplaceLane(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt16x8Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8Equal(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8NotEqual(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8LessThan(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt16x8LessThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt16x8GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt16x8GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint16x8GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint16x8GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitCreateInt8x16(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16ExtractLane(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt8x16ReplaceLane(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt8x16Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16Equal(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16NotEqual(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16LessThan(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt8x16LessThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt8x16GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitInt8x16GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint8x16GreaterThan(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitUint8x16GreaterThanOrEqual(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }

4
src/compiler/machine-graph-verifier.cc
View File

@ -208,6 +208,8 @@ class MachineRepresentationInferrer {
case IrOpcode::kTruncateFloat32ToUint32:
case IrOpcode::kBitcastFloat32ToInt32:
case IrOpcode::kInt32x4ExtractLane:
case IrOpcode::kInt16x8ExtractLane:
case IrOpcode::kInt8x16ExtractLane:
case IrOpcode::kInt32Constant:
case IrOpcode::kRelocatableInt32Constant:
case IrOpcode::kTruncateFloat64ToWord32:
@ -352,6 +354,8 @@ class MachineRepresentationChecker {
CheckValueInputForInt64Op(node, 1);
break;
case IrOpcode::kInt32x4ExtractLane:
case IrOpcode::kInt16x8ExtractLane:
case IrOpcode::kInt8x16ExtractLane:
CheckValueInputRepresentationIs(node, 0,
MachineRepresentation::kSimd128);
break;

48
src/compiler/machine-operator.cc
View File

@ -221,8 +221,6 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
V(Word32PairShr, Operator::kNoProperties, 3, 0, 2) \
V(Word32PairSar, Operator::kNoProperties, 3, 0, 2) \
V(CreateFloat32x4, Operator::kNoProperties, 4, 0, 1) \
V(Float32x4ExtractLane, Operator::kNoProperties, 2, 0, 1) \
V(Float32x4ReplaceLane, Operator::kNoProperties, 3, 0, 1) \
V(Float32x4Abs, Operator::kNoProperties, 1, 0, 1) \
V(Float32x4Neg, Operator::kNoProperties, 1, 0, 1) \
V(Float32x4Sqrt, Operator::kNoProperties, 1, 0, 1) \
@ -245,8 +243,6 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
V(Float32x4FromInt32x4, Operator::kNoProperties, 1, 0, 1) \
V(Float32x4FromUint32x4, Operator::kNoProperties, 1, 0, 1) \
V(CreateInt32x4, Operator::kNoProperties, 4, 0, 1) \
V(Int32x4ExtractLane, Operator::kNoProperties, 2, 0, 1) \
V(Int32x4ReplaceLane, Operator::kNoProperties, 3, 0, 1) \
V(Int32x4Neg, Operator::kNoProperties, 1, 0, 1) \
V(Int32x4Add, Operator::kCommutative, 2, 0, 1) \
V(Int32x4Sub, Operator::kNoProperties, 2, 0, 1) \
@ -285,8 +281,6 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
V(Bool32x4Equal, Operator::kCommutative, 2, 0, 1) \
V(Bool32x4NotEqual, Operator::kCommutative, 2, 0, 1) \
V(CreateInt16x8, Operator::kNoProperties, 8, 0, 1) \
V(Int16x8ExtractLane, Operator::kNoProperties, 2, 0, 1) \
V(Int16x8ReplaceLane, Operator::kNoProperties, 3, 0, 1) \
V(Int16x8Neg, Operator::kNoProperties, 1, 0, 1) \
V(Int16x8Add, Operator::kCommutative, 2, 0, 1) \
V(Int16x8AddSaturate, Operator::kCommutative, 2, 0, 1) \
@ -330,8 +324,6 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
V(Bool16x8Equal, Operator::kCommutative, 2, 0, 1) \
V(Bool16x8NotEqual, Operator::kCommutative, 2, 0, 1) \
V(CreateInt8x16, Operator::kNoProperties, 16, 0, 1) \
V(Int8x16ExtractLane, Operator::kNoProperties, 2, 0, 1) \
V(Int8x16ReplaceLane, Operator::kNoProperties, 3, 0, 1) \
V(Int8x16Neg, Operator::kNoProperties, 1, 0, 1) \
V(Int8x16Add, Operator::kCommutative, 2, 0, 1) \
V(Int8x16AddSaturate, Operator::kCommutative, 2, 0, 1) \
@ -458,6 +450,12 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
V(kWord16) \
V(kWord32)
#define SIMD_LANE_OP_LIST(V) \
V(Float32x4, 4) \
V(Int32x4, 4) \
V(Int16x8, 8) \
V(Int8x16, 16)
#define STACK_SLOT_CACHED_SIZES_LIST(V) V(4) V(8) V(16)
struct StackSlotOperator : public Operator1<int> {
@ -634,6 +632,24 @@ struct MachineOperatorGlobalCache {
ATOMIC_REPRESENTATION_LIST(ATOMIC_STORE)
#undef STORE
#define SIMD_LANE_OPS(Name, lane_count) \
struct Name##ExtractLaneOperator final : public Operator1<int> { \
static int lane_number; \
Name##ExtractLaneOperator() \
: Operator1<int>(IrOpcode::k##Name##ExtractLane, Operator::kPure, \
"ExtractLane", 1, 0, 0, 1, 0, 0, lane_number++) {} \
}; \
struct Name##ReplaceLaneOperator final : public Operator1<int> { \
static int lane_number; \
Name##ReplaceLaneOperator() \
: Operator1<int>(IrOpcode::k##Name##ReplaceLane, Operator::kPure, \
"ReplaceLane", 2, 0, 0, 1, 0, 0, lane_number++) {} \
}; \
Name##ExtractLaneOperator k##Name##ExtractLane[lane_count]; \
Name##ReplaceLaneOperator k##Name##ReplaceLane[lane_count];
SIMD_LANE_OP_LIST(SIMD_LANE_OPS)
#undef SIMD_LANE_OPS
struct DebugBreakOperator : public Operator {
DebugBreakOperator()
: Operator(IrOpcode::kDebugBreak, Operator::kNoThrow, "DebugBreak", 0,
@ -861,6 +877,22 @@ const Operator* MachineOperatorBuilder::AtomicStore(MachineRepresentation rep) {
return nullptr;
}
#define SIMD_LANE_OPS(Name, lane_count) \
const Operator* MachineOperatorBuilder::Name##ExtractLane( \
int32_t lane_number) { \
DCHECK(0 <= lane_number && lane_number < lane_count); \
return &cache_.k##Name##ExtractLane[lane_number]; \
} \
const Operator* MachineOperatorBuilder::Name##ReplaceLane( \
int32_t lane_number) { \
DCHECK(0 <= lane_number && lane_number < lane_count); \
return &cache_.k##Name##ReplaceLane[lane_number]; \
} \
int MachineOperatorGlobalCache::Name##ExtractLaneOperator::lane_number = 0; \
int MachineOperatorGlobalCache::Name##ReplaceLaneOperator::lane_number = 0;
SIMD_LANE_OP_LIST(SIMD_LANE_OPS)
#undef SIMD_LANE_OPS
} // namespace compiler
} // namespace internal
} // namespace v8

16
src/compiler/machine-operator.h
View File

@ -426,8 +426,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
// SIMD operators.
const Operator* CreateFloat32x4();
const Operator* Float32x4ExtractLane();
const Operator* Float32x4ReplaceLane();
const Operator* Float32x4ExtractLane(int32_t);
const Operator* Float32x4ReplaceLane(int32_t);
const Operator* Float32x4Abs();
const Operator* Float32x4Neg();
const Operator* Float32x4Sqrt();
@ -451,8 +451,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* Float32x4FromUint32x4();
const Operator* CreateInt32x4();
const Operator* Int32x4ExtractLane();
const Operator* Int32x4ReplaceLane();
const Operator* Int32x4ExtractLane(int32_t);
const Operator* Int32x4ReplaceLane(int32_t);
const Operator* Int32x4Neg();
const Operator* Int32x4Add();
const Operator* Int32x4Sub();
@ -494,8 +494,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* Bool32x4NotEqual();
const Operator* CreateInt16x8();
const Operator* Int16x8ExtractLane();
const Operator* Int16x8ReplaceLane();
const Operator* Int16x8ExtractLane(int32_t);
const Operator* Int16x8ReplaceLane(int32_t);
const Operator* Int16x8Neg();
const Operator* Int16x8Add();
const Operator* Int16x8AddSaturate();
@ -542,8 +542,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* Bool16x8NotEqual();
const Operator* CreateInt8x16();
const Operator* Int8x16ExtractLane();
const Operator* Int8x16ReplaceLane();
const Operator* Int8x16ExtractLane(int32_t);
const Operator* Int8x16ReplaceLane(int32_t);
const Operator* Int8x16Neg();
const Operator* Int8x16Add();
const Operator* Int8x16AddSaturate();

173
src/compiler/wasm-compiler.cc
View File

@ -3384,21 +3384,166 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
case wasm::kExprI32x4UConvertF32x4:
return graph()->NewNode(jsgraph()->machine()->Uint32x4FromFloat32x4(),
inputs[0]);
case wasm::kExprI32x4Neg:
return graph()->NewNode(jsgraph()->machine()->Int32x4Neg(), inputs[0]);
case wasm::kExprI32x4Add:
return graph()->NewNode(jsgraph()->machine()->Int32x4Add(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Sub:
return graph()->NewNode(jsgraph()->machine()->Int32x4Sub(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Mul:
return graph()->NewNode(jsgraph()->machine()->Int32x4Mul(), inputs[0],
inputs[1]);
case wasm::kExprI32x4MinS:
return graph()->NewNode(jsgraph()->machine()->Int32x4Min(), inputs[0],
inputs[1]);
case wasm::kExprI32x4MaxS:
return graph()->NewNode(jsgraph()->machine()->Int32x4Max(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Eq:
return graph()->NewNode(jsgraph()->machine()->Int32x4Equal(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Ne:
return graph()->NewNode(jsgraph()->machine()->Int32x4NotEqual(),
inputs[0], inputs[1]);
case wasm::kExprI32x4LtS:
return graph()->NewNode(jsgraph()->machine()->Int32x4GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI32x4LeS:
return graph()->NewNode(jsgraph()->machine()->Int32x4GreaterThanOrEqual(),
inputs[1], inputs[0]);
case wasm::kExprI32x4GtS:
return graph()->NewNode(jsgraph()->machine()->Int32x4GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI32x4GeS:
return graph()->NewNode(jsgraph()->machine()->Int32x4GreaterThanOrEqual(),
inputs[0], inputs[1]);
case wasm::kExprI32x4LtU:
return graph()->NewNode(jsgraph()->machine()->Uint32x4GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI32x4LeU:
return graph()->NewNode(
jsgraph()->machine()->Uint32x4GreaterThanOrEqual(), inputs[1],
inputs[0]);
case wasm::kExprI32x4GtU:
return graph()->NewNode(jsgraph()->machine()->Uint32x4GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI32x4GeU:
return graph()->NewNode(
jsgraph()->machine()->Uint32x4GreaterThanOrEqual(), inputs[0],
inputs[1]);
case wasm::kExprS32x4Select:
return graph()->NewNode(jsgraph()->machine()->Simd32x4Select(), inputs[0],
inputs[1], inputs[2]);
case wasm::kExprI16x8Splat:
return graph()->NewNode(jsgraph()->machine()->CreateInt16x8(), inputs[0],
inputs[0], inputs[0], inputs[0], inputs[0],
inputs[0], inputs[0], inputs[0]);
case wasm::kExprI16x8Neg:
return graph()->NewNode(jsgraph()->machine()->Int16x8Neg(), inputs[0]);
case wasm::kExprI16x8Add:
return graph()->NewNode(jsgraph()->machine()->Int16x8Add(), inputs[0],
inputs[1]);
case wasm::kExprI16x8Sub:
return graph()->NewNode(jsgraph()->machine()->Int16x8Sub(), inputs[0],
inputs[1]);
case wasm::kExprI16x8Mul:
return graph()->NewNode(jsgraph()->machine()->Int16x8Mul(), inputs[0],
inputs[1]);
case wasm::kExprI16x8MinS:
return graph()->NewNode(jsgraph()->machine()->Int16x8Min(), inputs[0],
inputs[1]);
case wasm::kExprI16x8MaxS:
return graph()->NewNode(jsgraph()->machine()->Int16x8Max(), inputs[0],
inputs[1]);
case wasm::kExprI16x8Eq:
return graph()->NewNode(jsgraph()->machine()->Int16x8Equal(), inputs[0],
inputs[1]);
case wasm::kExprI16x8Ne:
return graph()->NewNode(jsgraph()->machine()->Int16x8NotEqual(),
inputs[0], inputs[1]);
case wasm::kExprI16x8LtS:
return graph()->NewNode(jsgraph()->machine()->Int16x8GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI16x8LeS:
return graph()->NewNode(jsgraph()->machine()->Int16x8GreaterThanOrEqual(),
inputs[1], inputs[0]);
case wasm::kExprI16x8GtS:
return graph()->NewNode(jsgraph()->machine()->Int16x8GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI16x8GeS:
return graph()->NewNode(jsgraph()->machine()->Int16x8GreaterThanOrEqual(),
inputs[0], inputs[1]);
case wasm::kExprI16x8LtU:
return graph()->NewNode(jsgraph()->machine()->Uint16x8GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI16x8LeU:
return graph()->NewNode(
jsgraph()->machine()->Uint16x8GreaterThanOrEqual(), inputs[1],
inputs[0]);
case wasm::kExprI16x8GtU:
return graph()->NewNode(jsgraph()->machine()->Uint16x8GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI16x8GeU:
return graph()->NewNode(
jsgraph()->machine()->Uint16x8GreaterThanOrEqual(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Splat:
return graph()->NewNode(jsgraph()->machine()->CreateInt8x16(), inputs[0],
inputs[0], inputs[0], inputs[0], inputs[0],
inputs[0], inputs[0], inputs[0], inputs[0],
inputs[0], inputs[0], inputs[0], inputs[0],
inputs[0], inputs[0], inputs[0]);
case wasm::kExprI8x16Neg:
return graph()->NewNode(jsgraph()->machine()->Int8x16Neg(), inputs[0]);
case wasm::kExprI8x16Add:
return graph()->NewNode(jsgraph()->machine()->Int8x16Add(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Sub:
return graph()->NewNode(jsgraph()->machine()->Int8x16Sub(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Mul:
return graph()->NewNode(jsgraph()->machine()->Int8x16Mul(), inputs[0],
inputs[1]);
case wasm::kExprI8x16MinS:
return graph()->NewNode(jsgraph()->machine()->Int8x16Min(), inputs[0],
inputs[1]);
case wasm::kExprI8x16MaxS:
return graph()->NewNode(jsgraph()->machine()->Int8x16Max(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Eq:
return graph()->NewNode(jsgraph()->machine()->Int8x16Equal(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Ne:
return graph()->NewNode(jsgraph()->machine()->Int8x16NotEqual(),
inputs[0], inputs[1]);
case wasm::kExprI8x16LtS:
return graph()->NewNode(jsgraph()->machine()->Int8x16GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI8x16LeS:
return graph()->NewNode(jsgraph()->machine()->Int8x16GreaterThanOrEqual(),
inputs[1], inputs[0]);
case wasm::kExprI8x16GtS:
return graph()->NewNode(jsgraph()->machine()->Int8x16GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI8x16GeS:
return graph()->NewNode(jsgraph()->machine()->Int8x16GreaterThanOrEqual(),
inputs[0], inputs[1]);
case wasm::kExprI8x16LtU:
return graph()->NewNode(jsgraph()->machine()->Uint8x16GreaterThan(),
inputs[1], inputs[0]);
case wasm::kExprI8x16LeU:
return graph()->NewNode(
jsgraph()->machine()->Uint8x16GreaterThanOrEqual(), inputs[1],
inputs[0]);
case wasm::kExprI8x16GtU:
return graph()->NewNode(jsgraph()->machine()->Uint8x16GreaterThan(),
inputs[0], inputs[1]);
case wasm::kExprI8x16GeU:
return graph()->NewNode(
jsgraph()->machine()->Uint8x16GreaterThanOrEqual(), inputs[0],
inputs[1]);
default:
return graph()->NewNode(UnsupportedOpcode(opcode), nullptr);
}
@ -3408,17 +3553,29 @@ Node* WasmGraphBuilder::SimdLaneOp(wasm::WasmOpcode opcode, uint8_t lane,
const NodeVector& inputs) {
has_simd_ = true;
switch (opcode) {
case wasm::kExprI32x4ExtractLane:
return graph()->NewNode(jsgraph()->common()->Int32x4ExtractLane(lane),
inputs[0]);
case wasm::kExprI32x4ReplaceLane:
return graph()->NewNode(jsgraph()->common()->Int32x4ReplaceLane(lane),
inputs[0], inputs[1]);
case wasm::kExprF32x4ExtractLane:
return graph()->NewNode(jsgraph()->common()->Float32x4ExtractLane(lane),
return graph()->NewNode(jsgraph()->machine()->Float32x4ExtractLane(lane),
inputs[0]);
case wasm::kExprF32x4ReplaceLane:
return graph()->NewNode(jsgraph()->common()->Float32x4ReplaceLane(lane),
return graph()->NewNode(jsgraph()->machine()->Float32x4ReplaceLane(lane),
inputs[0], inputs[1]);
case wasm::kExprI32x4ExtractLane:
return graph()->NewNode(jsgraph()->machine()->Int32x4ExtractLane(lane),
inputs[0]);
case wasm::kExprI32x4ReplaceLane:
return graph()->NewNode(jsgraph()->machine()->Int32x4ReplaceLane(lane),
inputs[0], inputs[1]);
case wasm::kExprI16x8ExtractLane:
return graph()->NewNode(jsgraph()->machine()->Int16x8ExtractLane(lane),
inputs[0]);
case wasm::kExprI16x8ReplaceLane:
return graph()->NewNode(jsgraph()->machine()->Int16x8ReplaceLane(lane),
inputs[0], inputs[1]);
case wasm::kExprI8x16ExtractLane:
return graph()->NewNode(jsgraph()->machine()->Int8x16ExtractLane(lane),
inputs[0]);
case wasm::kExprI8x16ReplaceLane:
return graph()->NewNode(jsgraph()->machine()->Int8x16ReplaceLane(lane),
inputs[0], inputs[1]);
default:
return graph()->NewNode(UnsupportedOpcode(opcode), nullptr);

47
src/wasm/function-body-decoder.cc
View File

@ -348,9 +348,30 @@ class WasmDecoder : public Decoder {
return true;
}
inline bool Validate(const byte* pc, LaneOperand& operand) {
if (operand.lane < 0 || operand.lane > 3) {
error(pc_, pc_ + 2, "invalid extract lane value");
inline bool Validate(const byte* pc, WasmOpcode opcode,
LaneOperand& operand) {
uint8_t num_lanes = 0;
switch (opcode) {
case kExprF32x4ExtractLane:
case kExprF32x4ReplaceLane:
case kExprI32x4ExtractLane:
case kExprI32x4ReplaceLane:
num_lanes = 4;
break;
case kExprI16x8ExtractLane:
case kExprI16x8ReplaceLane:
num_lanes = 8;
break;
case kExprI8x16ExtractLane:
case kExprI8x16ReplaceLane:
num_lanes = 16;
break;
default:
UNREACHABLE();
break;
}
if (operand.lane < 0 || operand.lane >= num_lanes) {
error(pc_, pc_ + 2, "invalid lane value");
return false;
} else {
return true;
@ -1338,7 +1359,7 @@ class WasmFullDecoder : public WasmDecoder {
unsigned ExtractLane(WasmOpcode opcode, ValueType type) {
LaneOperand operand(this, pc_);
if (Validate(pc_, operand)) {
if (Validate(pc_, opcode, operand)) {
compiler::NodeVector inputs(1, zone_);
inputs[0] = Pop(0, ValueType::kSimd128).node;
TFNode* node = BUILD(SimdLaneOp, opcode, operand.lane, inputs);
@ -1349,7 +1370,7 @@ class WasmFullDecoder : public WasmDecoder {
unsigned ReplaceLane(WasmOpcode opcode, ValueType type) {
LaneOperand operand(this, pc_);
if (Validate(pc_, operand)) {
if (Validate(pc_, opcode, operand)) {
compiler::NodeVector inputs(2, zone_);
inputs[1] = Pop(1, type).node;
inputs[0] = Pop(0, ValueType::kSimd128).node;
@ -1362,22 +1383,26 @@ class WasmFullDecoder : public WasmDecoder {
unsigned DecodeSimdOpcode(WasmOpcode opcode) {
unsigned len = 0;
switch (opcode) {
case kExprI32x4ExtractLane: {
len = ExtractLane(opcode, ValueType::kWord32);
break;
}
case kExprF32x4ExtractLane: {
len = ExtractLane(opcode, ValueType::kFloat32);
break;
}
case kExprI32x4ReplaceLane: {
len = ReplaceLane(opcode, ValueType::kWord32);
case kExprI32x4ExtractLane:
case kExprI16x8ExtractLane:
case kExprI8x16ExtractLane: {
len = ExtractLane(opcode, ValueType::kWord32);
break;
}
case kExprF32x4ReplaceLane: {
len = ReplaceLane(opcode, ValueType::kFloat32);
break;
}
case kExprI32x4ReplaceLane:
case kExprI16x8ReplaceLane:
case kExprI8x16ReplaceLane: {
len = ReplaceLane(opcode, ValueType::kWord32);
break;
}
default: {
FunctionSig* sig = WasmOpcodes::Signature(opcode);
if (sig != nullptr) {

12
src/wasm/wasm-macro-gen.h
View File

@ -650,6 +650,18 @@ class LocalDeclEncoder {
#define WASM_SIMD_I32x4_ADD(x, y) x, y, kSimdPrefix, kExprI32x4Add & 0xff
#define WASM_SIMD_I32x4_SUB(x, y) x, y, kSimdPrefix, kExprI32x4Sub & 0xff
#define WASM_SIMD_I16x8_SPLAT(x) x, kSimdPrefix, kExprI16x8Splat & 0xff
#define WASM_SIMD_I16x8_EXTRACT_LANE(lane, x) \
x, kSimdPrefix, kExprI16x8ExtractLane & 0xff, static_cast<byte>(lane)
#define WASM_SIMD_I16x8_REPLACE_LANE(lane, x, y) \
x, y, kSimdPrefix, kExprI16x8ReplaceLane & 0xff, static_cast<byte>(lane)
#define WASM_SIMD_I8x16_SPLAT(x) x, kSimdPrefix, kExprI8x16Splat & 0xff
#define WASM_SIMD_I8x16_EXTRACT_LANE(lane, x) \
x, kSimdPrefix, kExprI8x16ExtractLane & 0xff, static_cast<byte>(lane)
#define WASM_SIMD_I8x16_REPLACE_LANE(lane, x, y) \
x, y, kSimdPrefix, kExprI8x16ReplaceLane & 0xff, static_cast<byte>(lane)
#define SIG_ENTRY_v_v kWasmFunctionTypeForm, 0, 0
#define SIZEOF_SIG_ENTRY_v_v 3

14
test/cctest/compiler/value-helper.h
View File

@ -300,6 +300,18 @@ class ValueHelper {
return std::vector<double>(&values[0], &values[arraysize(values)]);
}
static const std::vector<int16_t> int16_vector() {
static const int16_t kValues[] = {
0, 1, 2, INT16_MAX - 1, INT16_MAX, INT16_MIN, INT16_MIN + 1, -2, -1};
return std::vector<int16_t>(&kValues[0], &kValues[arraysize(kValues)]);
}
static const std::vector<int8_t> int8_vector() {
static const int8_t kValues[] = {
0, 1, 2, INT8_MAX - 1, INT8_MAX, INT8_MIN, INT8_MIN + 1, -2, -1};
return std::vector<int8_t>(&kValues[0], &kValues[arraysize(kValues)]);
}
static const std::vector<uint32_t> ror_vector() {
static const uint32_t kValues[31] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
@ -317,6 +329,8 @@ class ValueHelper {
#define FOR_INT32_INPUTS(var) FOR_INPUTS(int32_t, int32, var)
#define FOR_UINT32_INPUTS(var) FOR_INPUTS(uint32_t, uint32, var)
#define FOR_INT16_INPUTS(var) FOR_INPUTS(int16_t, int16, var)
#define FOR_INT8_INPUTS(var) FOR_INPUTS(int8_t, int8, var)
#define FOR_INT64_INPUTS(var) FOR_INPUTS(int64_t, int64, var)
#define FOR_UINT64_INPUTS(var) FOR_INPUTS(uint64_t, uint64, var)
#define FOR_FLOAT32_INPUTS(var) FOR_INPUTS(float, float32, var)

506
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -18,8 +18,21 @@ namespace {
typedef float (*FloatUnOp)(float);
typedef float (*FloatBinOp)(float, float);
typedef int32_t (*FloatCompareOp)(float, float);
typedef int32_t (*Int32UnOp)(int32_t);
typedef int32_t (*Int32BinOp)(int32_t, int32_t);
typedef int16_t (*Int16UnOp)(int16_t);
typedef int16_t (*Int16BinOp)(int16_t, int16_t);
typedef int8_t (*Int8UnOp)(int8_t);
typedef int8_t (*Int8BinOp)(int8_t, int8_t);
#if V8_TARGET_ARCH_ARM
// Floating point specific value functions.
int32_t Equal(float a, float b) { return a == b ? -1 : 0; }
int32_t NotEqual(float a, float b) { return a != b ? -1 : 0; }
#endif // V8_TARGET_ARCH_ARM
// Generic expected value functions.
template <typename T>
T Negate(T a) {
return -a;
@ -36,20 +49,63 @@ T Sub(T a, T b) {
}
template <typename T>
int32_t Equal(T a, T b) {
return a == b ? 0xFFFFFFFF : 0;
T Mul(T a, T b) {
return a * b;
}
template <typename T>
int32_t NotEqual(T a, T b) {
return a != b ? 0xFFFFFFFF : 0;
T Equal(T a, T b) {
return a == b ? -1 : 0;
}
#if V8_TARGET_ARCH_ARM
int32_t Equal(float a, float b) { return a == b ? 0xFFFFFFFF : 0; }
template <typename T>
T NotEqual(T a, T b) {
return a != b ? -1 : 0;
}
int32_t NotEqual(float a, float b) { return a != b ? 0xFFFFFFFF : 0; }
#endif // V8_TARGET_ARCH_ARM
template <typename T>
T Greater(T a, T b) {
return a > b ? -1 : 0;
}
template <typename T>
T GreaterEqual(T a, T b) {
return a >= b ? -1 : 0;
}
template <typename T>
T Less(T a, T b) {
return a < b ? -1 : 0;
}
template <typename T>
T LessEqual(T a, T b) {
return a <= b ? -1 : 0;
}
template <typename T>
T UnsignedGreater(T a, T b) {
using UnsignedT = typename std::make_unsigned<T>::type;
return static_cast<UnsignedT>(a) > static_cast<UnsignedT>(b) ? -1 : 0;
}
template <typename T>
T UnsignedGreaterEqual(T a, T b) {
using UnsignedT = typename std::make_unsigned<T>::type;
return static_cast<UnsignedT>(a) >= static_cast<UnsignedT>(b) ? -1 : 0;
}
template <typename T>
T UnsignedLess(T a, T b) {
using UnsignedT = typename std::make_unsigned<T>::type;
return static_cast<UnsignedT>(a) < static_cast<UnsignedT>(b) ? -1 : 0;
}
template <typename T>
T UnsignedLessEqual(T a, T b) {
using UnsignedT = typename std::make_unsigned<T>::type;
return static_cast<UnsignedT>(a) <= static_cast<UnsignedT>(b) ? -1 : 0;
}
} // namespace
@ -74,6 +130,44 @@ int32_t NotEqual(float a, float b) { return a != b ? 0xFFFFFFFF : 0; }
#define WASM_SIMD_CHECK_SPLAT4(TYPE, value, LANE_TYPE, lv) \
WASM_SIMD_CHECK4(TYPE, value, LANE_TYPE, lv, lv, lv, lv)
#define WASM_SIMD_CHECK8(TYPE, value, LANE_TYPE, lv0, lv1, lv2, lv3, lv4, lv5, \
lv6, lv7) \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv0, 0) \
, WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv1, 1), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv2, 2), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv3, 3), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv4, 4), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv5, 5), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv6, 6), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv7, 7)
#define WASM_SIMD_CHECK_SPLAT8(TYPE, value, LANE_TYPE, lv) \
WASM_SIMD_CHECK8(TYPE, value, LANE_TYPE, lv, lv, lv, lv, lv, lv, lv, lv)
#define WASM_SIMD_CHECK16(TYPE, value, LANE_TYPE, lv0, lv1, lv2, lv3, lv4, \
lv5, lv6, lv7, lv8, lv9, lv10, lv11, lv12, lv13, \
lv14, lv15) \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv0, 0) \
, WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv1, 1), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv2, 2), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv3, 3), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv4, 4), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv5, 5), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv6, 6), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv7, 7), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv8, 8), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv9, 9), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv10, 10), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv11, 11), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv12, 12), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv13, 13), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv14, 14), \
WASM_SIMD_CHECK_LANE(TYPE, value, LANE_TYPE, lv15, 15)
#define WASM_SIMD_CHECK_SPLAT16(TYPE, value, LANE_TYPE, lv) \
WASM_SIMD_CHECK16(TYPE, value, LANE_TYPE, lv, lv, lv, lv, lv, lv, lv, lv, \
lv, lv, lv, lv, lv, lv, lv, lv)
#define WASM_SIMD_CHECK_F32_LANE(TYPE, value, lane_value, lane_index) \
WASM_IF( \
WASM_I32_NE(WASM_I32_REINTERPRET_F32(WASM_GET_LOCAL(lane_value)), \
@ -341,6 +435,210 @@ WASM_EXEC_TEST(I32x4ReplaceLane) {
#if V8_TARGET_ARCH_ARM
WASM_EXEC_TEST(I16x8Splat) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t> r(kExecuteCompiled);
byte lane_val = 0;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(WASM_SET_LOCAL(simd, WASM_SIMD_I16x8_SPLAT(
WASM_GET_LOCAL(lane_val))),
WASM_SIMD_CHECK_SPLAT8(I16x8, simd, I32, lane_val),
WASM_RETURN1(WASM_ONE)));
FOR_INT16_INPUTS(i) { CHECK_EQ(1, r.Call(*i)); }
}
WASM_EXEC_TEST(I16x8ReplaceLane) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte old_val = 0;
byte new_val = 1;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd,
WASM_SIMD_I16x8_SPLAT(WASM_GET_LOCAL(old_val))),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(0, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(1, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, old_val,
old_val, old_val, old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(2, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, new_val,
old_val, old_val, old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(3, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, new_val,
new_val, old_val, old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(4, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, new_val,
new_val, new_val, old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(5, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(6, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK8(I16x8, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I16x8_REPLACE_LANE(7, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK_SPLAT8(I16x8, simd, I32, new_val),
WASM_RETURN1(WASM_ONE)));
CHECK_EQ(1, r.Call(1, 2));
}
WASM_EXEC_TEST(I8x16Splat) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t> r(kExecuteCompiled);
byte lane_val = 0;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(WASM_SET_LOCAL(simd, WASM_SIMD_I8x16_SPLAT(
WASM_GET_LOCAL(lane_val))),
WASM_SIMD_CHECK_SPLAT8(I8x16, simd, I32, lane_val),
WASM_RETURN1(WASM_ONE)));
FOR_INT8_INPUTS(i) { CHECK_EQ(1, r.Call(*i)); }
}
WASM_EXEC_TEST(I8x16ReplaceLane) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte old_val = 0;
byte new_val = 1;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd,
WASM_SIMD_I8x16_SPLAT(WASM_GET_LOCAL(old_val))),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(0, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(1, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(2, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(3, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(4, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, old_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(5, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, old_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(6, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, old_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(7, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
old_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(8, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, old_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(9, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, old_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(10, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, new_val, old_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(11, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, old_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(12, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
old_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(13, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, old_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(14, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK16(I8x16, simd, I32, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, new_val, new_val, new_val,
new_val, new_val, old_val),
WASM_SET_LOCAL(
simd, WASM_SIMD_I8x16_REPLACE_LANE(15, WASM_GET_LOCAL(simd),
WASM_GET_LOCAL(new_val))),
WASM_SIMD_CHECK_SPLAT16(I8x16, simd, I32, new_val),
WASM_RETURN1(WASM_ONE)));
CHECK_EQ(1, r.Call(1, 2));
}
// Determines if conversion from float to int will be valid.
bool CanRoundToZeroAndConvert(double val, bool unsigned_integer) {
const double max_uint = static_cast<double>(0xffffffffu);
@ -407,6 +705,24 @@ WASM_EXEC_TEST(I32x4FromFloat32x4) {
CHECK_EQ(1, r.Call(*i, signed_value, unsigned_value));
}
}
void RunI32x4UnOpTest(WasmOpcode simd_op, Int32UnOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte a = 0;
byte expected = 1;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd, WASM_SIMD_I32x4_SPLAT(WASM_GET_LOCAL(a))),
WASM_SET_LOCAL(
simd, WASM_SIMD_UNOP(simd_op & 0xffu, WASM_GET_LOCAL(simd))),
WASM_SIMD_CHECK_SPLAT4(I32x4, simd, I32, expected),
WASM_RETURN1(WASM_ONE)));
FOR_INT32_INPUTS(i) { CHECK_EQ(1, r.Call(*i, expected_op(*i))); }
}
WASM_EXEC_TEST(I32x4Neg) { RunI32x4UnOpTest(kExprI32x4Neg, Negate); }
#endif // V8_TARGET_ARCH_ARM
void RunI32x4BinOpTest(WasmOpcode simd_op, Int32BinOp expected_op) {
@ -436,7 +752,181 @@ WASM_EXEC_TEST(I32x4Add) { RunI32x4BinOpTest(kExprI32x4Add, Add); }
WASM_EXEC_TEST(I32x4Sub) { RunI32x4BinOpTest(kExprI32x4Sub, Sub); }
#if V8_TARGET_ARCH_ARM
WASM_EXEC_TEST(I32x4Mul) { RunI32x4BinOpTest(kExprI32x4Mul, Mul); }
WASM_EXEC_TEST(I32x4Equal) { RunI32x4BinOpTest(kExprI32x4Eq, Equal); }
WASM_EXEC_TEST(I32x4NotEqual) { RunI32x4BinOpTest(kExprI32x4Ne, NotEqual); }
WASM_EXEC_TEST(I32x4Greater) { RunI32x4BinOpTest(kExprI32x4GtS, Greater); }
WASM_EXEC_TEST(I32x4GreaterEqual) {
RunI32x4BinOpTest(kExprI32x4GeS, GreaterEqual);
}
WASM_EXEC_TEST(I32x4Less) { RunI32x4BinOpTest(kExprI32x4LtS, Less); }
WASM_EXEC_TEST(I32x4LessEqual) { RunI32x4BinOpTest(kExprI32x4LeS, LessEqual); }
WASM_EXEC_TEST(Ui32x4Greater) {
RunI32x4BinOpTest(kExprI32x4GtU, UnsignedGreater);
}
WASM_EXEC_TEST(Ui32x4GreaterEqual) {
RunI32x4BinOpTest(kExprI32x4GeU, UnsignedGreaterEqual);
}
WASM_EXEC_TEST(Ui32x4Less) { RunI32x4BinOpTest(kExprI32x4LtU, UnsignedLess); }
WASM_EXEC_TEST(Ui32x4LessEqual) {
RunI32x4BinOpTest(kExprI32x4LeU, UnsignedLessEqual);
}
void RunI16x8UnOpTest(WasmOpcode simd_op, Int16UnOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte a = 0;
byte expected = 1;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd, WASM_SIMD_I16x8_SPLAT(WASM_GET_LOCAL(a))),
WASM_SET_LOCAL(
simd, WASM_SIMD_UNOP(simd_op & 0xffu, WASM_GET_LOCAL(simd))),
WASM_SIMD_CHECK_SPLAT8(I16x8, simd, I32, expected),
WASM_RETURN1(WASM_ONE)));
FOR_INT16_INPUTS(i) { CHECK_EQ(1, r.Call(*i, expected_op(*i))); }
}
WASM_EXEC_TEST(I16x8Neg) { RunI16x8UnOpTest(kExprI16x8Neg, Negate); }
void RunI16x8BinOpTest(WasmOpcode simd_op, Int16BinOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte a = 0;
byte b = 1;
byte expected = 2;
byte simd0 = r.AllocateLocal(kWasmS128);
byte simd1 = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd0, WASM_SIMD_I16x8_SPLAT(WASM_GET_LOCAL(a))),
WASM_SET_LOCAL(simd1, WASM_SIMD_I16x8_SPLAT(WASM_GET_LOCAL(b))),
WASM_SET_LOCAL(simd1, WASM_SIMD_BINOP(simd_op & 0xffu,
WASM_GET_LOCAL(simd0),
WASM_GET_LOCAL(simd1))),
WASM_SIMD_CHECK_SPLAT8(I16x8, simd1, I32, expected),
WASM_RETURN1(WASM_ONE)));
FOR_INT16_INPUTS(i) {
FOR_INT16_INPUTS(j) { CHECK_EQ(1, r.Call(*i, *j, expected_op(*i, *j))); }
}
}
WASM_EXEC_TEST(I16x8Add) { RunI16x8BinOpTest(kExprI16x8Add, Add); }
WASM_EXEC_TEST(I16x8Sub) { RunI16x8BinOpTest(kExprI16x8Sub, Sub); }
WASM_EXEC_TEST(I16x8Mul) { RunI16x8BinOpTest(kExprI16x8Mul, Mul); }
WASM_EXEC_TEST(I16x8Equal) { RunI16x8BinOpTest(kExprI16x8Eq, Equal); }
WASM_EXEC_TEST(I16x8NotEqual) { RunI16x8BinOpTest(kExprI16x8Ne, NotEqual); }
WASM_EXEC_TEST(I16x8Greater) { RunI16x8BinOpTest(kExprI16x8GtS, Greater); }
WASM_EXEC_TEST(I16x8GreaterEqual) {
RunI16x8BinOpTest(kExprI16x8GeS, GreaterEqual);
}
WASM_EXEC_TEST(I16x8Less) { RunI16x8BinOpTest(kExprI16x8LtS, Less); }
WASM_EXEC_TEST(I16x8LessEqual) { RunI16x8BinOpTest(kExprI16x8LeS, LessEqual); }
WASM_EXEC_TEST(Ui16x8Greater) {
RunI16x8BinOpTest(kExprI16x8GtU, UnsignedGreater);
}
WASM_EXEC_TEST(Ui16x8GreaterEqual) {
RunI16x8BinOpTest(kExprI16x8GeU, UnsignedGreaterEqual);
}
WASM_EXEC_TEST(Ui16x8Less) { RunI16x8BinOpTest(kExprI16x8LtU, UnsignedLess); }
WASM_EXEC_TEST(Ui16x8LessEqual) {
RunI16x8BinOpTest(kExprI16x8LeU, UnsignedLessEqual);
}
void RunI8x16UnOpTest(WasmOpcode simd_op, Int8UnOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte a = 0;
byte expected = 1;
byte simd = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd, WASM_SIMD_I8x16_SPLAT(WASM_GET_LOCAL(a))),
WASM_SET_LOCAL(
simd, WASM_SIMD_UNOP(simd_op & 0xffu, WASM_GET_LOCAL(simd))),
WASM_SIMD_CHECK_SPLAT16(I8x16, simd, I32, expected),
WASM_RETURN1(WASM_ONE)));
FOR_INT8_INPUTS(i) { CHECK_EQ(1, r.Call(*i, expected_op(*i))); }
}
WASM_EXEC_TEST(I8x16Neg) { RunI8x16UnOpTest(kExprI8x16Neg, Negate); }
void RunI8x16BinOpTest(WasmOpcode simd_op, Int8BinOp expected_op) {
FLAG_wasm_simd_prototype = true;
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled);
byte a = 0;
byte b = 1;
byte expected = 2;
byte simd0 = r.AllocateLocal(kWasmS128);
byte simd1 = r.AllocateLocal(kWasmS128);
BUILD(r, WASM_BLOCK(
WASM_SET_LOCAL(simd0, WASM_SIMD_I8x16_SPLAT(WASM_GET_LOCAL(a))),
WASM_SET_LOCAL(simd1, WASM_SIMD_I8x16_SPLAT(WASM_GET_LOCAL(b))),
WASM_SET_LOCAL(simd1, WASM_SIMD_BINOP(simd_op & 0xffu,
WASM_GET_LOCAL(simd0),
WASM_GET_LOCAL(simd1))),
WASM_SIMD_CHECK_SPLAT16(I8x16, simd1, I32, expected),
WASM_RETURN1(WASM_ONE)));
FOR_INT8_INPUTS(i) {
FOR_INT8_INPUTS(j) { CHECK_EQ(1, r.Call(*i, *j, expected_op(*i, *j))); }
}
}
WASM_EXEC_TEST(I8x16Add) { RunI8x16BinOpTest(kExprI8x16Add, Add); }
WASM_EXEC_TEST(I8x16Sub) { RunI8x16BinOpTest(kExprI8x16Sub, Sub); }
WASM_EXEC_TEST(I8x16Mul) { RunI8x16BinOpTest(kExprI8x16Mul, Mul); }
WASM_EXEC_TEST(I8x16Equal) { RunI8x16BinOpTest(kExprI8x16Eq, Equal); }
WASM_EXEC_TEST(I8x16NotEqual) { RunI8x16BinOpTest(kExprI8x16Ne, NotEqual); }
WASM_EXEC_TEST(I8x16Greater) { RunI8x16BinOpTest(kExprI8x16GtS, Greater); }
WASM_EXEC_TEST(I8x16GreaterEqual) {
RunI8x16BinOpTest(kExprI8x16GeS, GreaterEqual);
}
WASM_EXEC_TEST(I8x16Less) { RunI8x16BinOpTest(kExprI8x16LtS, Less); }
WASM_EXEC_TEST(I8x16LessEqual) { RunI8x16BinOpTest(kExprI8x16LeS, LessEqual); }
WASM_EXEC_TEST(Ui8x16Greater) {
RunI8x16BinOpTest(kExprI8x16GtU, UnsignedGreater);
}
WASM_EXEC_TEST(Ui8x16GreaterEqual) {
RunI8x16BinOpTest(kExprI8x16GeU, UnsignedGreaterEqual);
}
WASM_EXEC_TEST(Ui8x16Less) { RunI8x16BinOpTest(kExprI8x16LtU, UnsignedLess); }
WASM_EXEC_TEST(Ui8x16LessEqual) {
RunI8x16BinOpTest(kExprI8x16LeU, UnsignedLessEqual);
}
#endif // V8_TARGET_ARCH_ARM