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[wasm-simd] Implement v8x16.swizzle for ia32

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Bug: v8:8460
Change-Id: I9ac358eabd508d31034e11f28f583c5acbb0b0e2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1849205
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64202}
This commit is contained in:
Ng Zhi An 2019-10-09 13:49:11 -07:00 committed by Commit Bot
parent 3fdc88defb
commit c75b543ddb
7 changed files with 28 additions and 2 deletions
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1
src/codegen/ia32/macro-assembler-ia32.h
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@ -279,6 +279,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP3_XO(Packsswb, packsswb)
AVX_OP3_XO(Packuswb, packuswb)
AVX_OP3_XO(Paddusb, paddusb)
AVX_OP3_XO(Pcmpeqb, pcmpeqb)
AVX_OP3_XO(Pcmpeqw, pcmpeqw)
AVX_OP3_XO(Pcmpeqd, pcmpeqd)

13
src/compiler/backend/ia32/code-generator-ia32.cc
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@ -3535,6 +3535,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vxorps(dst, kScratchDoubleReg, i.InputSimd128Register(2));
break;
}
case kIA32S8x16Swizzle: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
XMMRegister dst = i.OutputSimd128Register();
XMMRegister mask = i.TempSimd128Register(0);
// Out-of-range indices should return 0, add 112 so that any value > 15
// saturates to 128 (top bit set), so pshufb will zero that lane.
__ Move(mask, (uint32_t)0x70707070);
__ Pshufd(mask, mask, 0x0);
__ Paddusb(mask, i.InputSimd128Register(1));
__ Pshufb(dst, mask);
break;
}
case kIA32S8x16Shuffle: {
XMMRegister dst = i.OutputSimd128Register();
Operand src0 = i.InputOperand(0);

1
src/compiler/backend/ia32/instruction-codes-ia32.h
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@ -330,6 +330,7 @@ namespace compiler {
V(AVXS128Xor) \
V(SSES128Select) \
V(AVXS128Select) \
V(IA32S8x16Swizzle) \
V(IA32S8x16Shuffle) \
V(IA32S32x4Swizzle) \
V(IA32S32x4Shuffle) \

1
src/compiler/backend/ia32/instruction-scheduler-ia32.cc
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@ -311,6 +311,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXS128Xor:
case kSSES128Select:
case kAVXS128Select:
case kIA32S8x16Swizzle:
case kIA32S8x16Shuffle:
case kIA32S32x4Swizzle:
case kIA32S32x4Shuffle:

8
src/compiler/backend/ia32/instruction-selector-ia32.cc
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@ -2569,6 +2569,14 @@ void InstructionSelector::VisitS8x16Shuffle(Node* node) {
Emit(opcode, 1, &dst, input_count, inputs, temp_count, temps);
}
void InstructionSelector::VisitS8x16Swizzle(Node* node) {
IA32OperandGenerator g(this);
InstructionOperand temps[] = {g.TempSimd128Register()};
Emit(kIA32S8x16Swizzle, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
arraysize(temps), temps);
}
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {

2
src/compiler/backend/instruction-selector.cc
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@ -2668,7 +2668,9 @@ void InstructionSelector::VisitI64x2MinS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MaxS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2MaxU(Node* node) { UNIMPLEMENTED(); }
#if !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_IA32
#endif // !V8_TARGET_ARCH_X64
void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }

4
test/cctest/wasm/test-run-wasm-simd.cc
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@ -2687,7 +2687,7 @@ WASM_SIMD_TEST(S8x16Concat) {
}
}
#ifdef V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32
struct SwizzleTestArgs {
const Shuffle input;
const Shuffle indices;
@ -2741,7 +2741,7 @@ WASM_SIMD_TEST(S8x16Swizzle) {
}
}
}
#endif // V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32
// Combine 3 shuffles a, b, and c by applying both a and b and then applying c
// to those two results.