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MIPS: [wasm] Implement Int32MulPair operator.

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Port 40bdbef975

Implement Int32MulPair operator for MIPS.

BUG=

Review URL: https://codereview.chromium.org/1848253002

Cr-Commit-Position: refs/heads/master@{#35256}
This commit is contained in:
marija.antic 2016-04-05 04:21:37 -07:00 committed by Commit bot
parent 47e0a39246
commit c9d1668f98
5 changed files with 49 additions and 1 deletions
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8
src/compiler/mips/code-generator-mips.cc
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@ -923,6 +923,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
case kMipsCmpD:
// Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
break;
case kMipsMulPair: {
__ Mulu(i.OutputRegister(1), i.OutputRegister(0), i.InputRegister(0),
i.InputRegister(2));
__ mul(kScratchReg, i.InputRegister(0), i.InputRegister(3));
__ mul(kScratchReg2, i.InputRegister(1), i.InputRegister(2));
__ Addu(i.OutputRegister(1), i.OutputRegister(1), kScratchReg);
__ Addu(i.OutputRegister(1), i.OutputRegister(1), kScratchReg2);
} break;
case kMipsAddD:
// TODO(plind): add special case: combine mult & add.
__ add_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),

1
src/compiler/mips/instruction-codes-mips.h
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@ -59,6 +59,7 @@ namespace compiler {
V(MipsSqrtD) \
V(MipsMaxD) \
V(MipsMinD) \
V(MipsMulPair) \
V(MipsFloat32RoundDown) \
V(MipsFloat32RoundTruncate) \
V(MipsFloat32RoundUp) \

12
src/compiler/mips/instruction-selector-mips.cc
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@ -399,7 +399,17 @@ void InstructionSelector::VisitInt32PairAdd(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32PairSub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32PairMul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitInt32PairMul(Node* node) {
MipsOperandGenerator g(this);
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
g.UseUniqueRegister(node->InputAt(2)),
g.UseUniqueRegister(node->InputAt(3))};
InstructionOperand outputs[] = {
g.DefineAsRegister(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Emit(kMipsMulPair, 2, outputs, 4, inputs);
}
void InstructionSelector::VisitWord32PairShl(Node* node) { UNIMPLEMENTED(); }

28
src/mips/macro-assembler-mips.cc
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@ -803,6 +803,34 @@ void MacroAssembler::Mul(Register rd_hi, Register rd_lo,
}
}
void MacroAssembler::Mulu(Register rd_hi, Register rd_lo, Register rs,
const Operand& rt) {
Register reg;
if (rt.is_reg()) {
reg = rt.rm();
} else {
DCHECK(!rs.is(at));
reg = at;
li(reg, rt);
}
if (!IsMipsArchVariant(kMips32r6)) {
multu(rs, reg);
mflo(rd_lo);
mfhi(rd_hi);
} else {
if (rd_lo.is(rs)) {
DCHECK(!rd_hi.is(rs));
DCHECK(!rd_hi.is(reg) && !rd_lo.is(reg));
muhu(rd_hi, rs, reg);
mulu(rd_lo, rs, reg);
} else {
DCHECK(!rd_hi.is(reg) && !rd_lo.is(reg));
mulu(rd_lo, rs, reg);
muhu(rd_hi, rs, reg);
}
}
}
void MacroAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {

1
src/mips/macro-assembler-mips.h
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@ -649,6 +649,7 @@ class MacroAssembler: public Assembler {
DEFINE_INSTRUCTION3(Div);
DEFINE_INSTRUCTION3(Mul);
DEFINE_INSTRUCTION3(Mulu);
DEFINE_INSTRUCTION(And);
DEFINE_INSTRUCTION(Or);