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Revert "MIPS64: Fix lithium arithmetic operations for integers to sign-extend result."

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This reverts commit 75744da268.

revert reason:
              octane failures.

BUG=

Review URL: https://codereview.chromium.org/1160143008

Cr-Commit-Position: refs/heads/master@{#28819}
This commit is contained in:
dusan.milosavljevic 2015-06-05 11:22:13 -07:00 committed by Commit bot
parent 25981994b7
commit ca0991c9bc
1 changed files with 14 additions and 14 deletions
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28
src/mips64/lithium-codegen-mips64.cc
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@ -1491,7 +1491,7 @@ void LCodeGen::DoMulI(LMulI* instr) {
DeoptimizeIf(gt, instr, Deoptimizer::kOverflow, scratch,
Operand(kMaxInt));
} else {
__ Subu(result, zero_reg, left);
__ Dsubu(result, zero_reg, left);
}
break;
case 0:
@ -1516,25 +1516,25 @@ void LCodeGen::DoMulI(LMulI* instr) {
if (base::bits::IsPowerOfTwo32(constant_abs)) {
int32_t shift = WhichPowerOf2(constant_abs);
__ sll(result, left, shift);
__ dsll(result, left, shift);
// Correct the sign of the result if the constant is negative.
if (constant < 0) __ Subu(result, zero_reg, result);
if (constant < 0) __ Dsubu(result, zero_reg, result);
} else if (base::bits::IsPowerOfTwo32(constant_abs - 1)) {
int32_t shift = WhichPowerOf2(constant_abs - 1);
__ sll(scratch, left, shift);
__ addu(result, scratch, left);
__ dsll(scratch, left, shift);
__ Daddu(result, scratch, left);
// Correct the sign of the result if the constant is negative.
if (constant < 0) __ Dsubu(result, zero_reg, result);
} else if (base::bits::IsPowerOfTwo32(constant_abs + 1)) {
int32_t shift = WhichPowerOf2(constant_abs + 1);
__ sll(scratch, left, shift);
__ Subu(result, scratch, left);
__ dsll(scratch, left, shift);
__ Dsubu(result, scratch, left);
// Correct the sign of the result if the constant is negative.
if (constant < 0) __ Dsubu(result, zero_reg, result);
} else {
// Generate standard code.
__ li(at, constant);
__ Mul(result, left, at);
__ Dmul(result, left, at);
}
}
@ -1558,9 +1558,9 @@ void LCodeGen::DoMulI(LMulI* instr) {
} else {
if (instr->hydrogen()->representation().IsSmi()) {
__ SmiUntag(result, left);
__ mul(result, result, right);
__ Dmul(result, result, right);
} else {
__ mul(result, left, right);
__ Dmul(result, left, right);
}
}
@ -1706,10 +1706,10 @@ void LCodeGen::DoSubI(LSubI* instr) {
if (!can_overflow) {
if (right->IsStackSlot()) {
Register right_reg = EmitLoadRegister(right, at);
__ Subu(ToRegister(result), ToRegister(left), Operand(right_reg));
__ Dsubu(ToRegister(result), ToRegister(left), Operand(right_reg));
} else {
DCHECK(right->IsRegister() || right->IsConstantOperand());
__ Subu(ToRegister(result), ToRegister(left), ToOperand(right));
__ Dsubu(ToRegister(result), ToRegister(left), ToOperand(right));
}
} else { // can_overflow.
Register overflow = scratch0();
@ -1898,10 +1898,10 @@ void LCodeGen::DoAddI(LAddI* instr) {
if (!can_overflow) {
if (right->IsStackSlot()) {
Register right_reg = EmitLoadRegister(right, at);
__ Addu(ToRegister(result), ToRegister(left), Operand(right_reg));
__ Daddu(ToRegister(result), ToRegister(left), Operand(right_reg));
} else {
DCHECK(right->IsRegister() || right->IsConstantOperand());
__ Addu(ToRegister(result), ToRegister(left), ToOperand(right));
__ Daddu(ToRegister(result), ToRegister(left), ToOperand(right));
}
} else { // can_overflow.
Register overflow = scratch0();