From cc77bd8234a8aa2293c7a028571ae5e8d4d13134 Mon Sep 17 00:00:00 2001 From: "dusan.simicic" Date: Thu, 22 Dec 2016 02:06:18 -0800 Subject: [PATCH] MIPS: Fix improper use of odd FP reg on mips32r6 Odd numbered floating-point register shouldn't be used as compare register on mips32r6 architecture. In case cpu switches to FRE mode, writes to odd numbered single-precision fp register will update upper part of even double-precision register, which will corrupt the even register. BUG= Review-Url: https://codereview.chromium.org/2591063003 Cr-Commit-Position: refs/heads/master@{#41916} --- src/mips/assembler-mips.h | 5 ++--- test/cctest/test-macro-assembler-mips.cc | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h index c03d9bd9ae..dec4c18889 100644 --- a/src/mips/assembler-mips.h +++ b/src/mips/assembler-mips.h @@ -68,7 +68,7 @@ namespace internal { #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ - V(f16) V(f18) V(f20) V(f22) V(f24) V(f26) + V(f16) V(f18) V(f20) V(f22) V(f24) // clang-format on // CPU Registers. @@ -282,8 +282,7 @@ const DoubleRegister f31 = {31}; #define kLithiumScratchDouble f30 #define kDoubleRegZero f28 // Used on mips32r6 for compare operations. -// We use the last non-callee saved odd register for O32 ABI -#define kDoubleCompareReg f19 +#define kDoubleCompareReg f26 // FPU (coprocessor 1) control registers. // Currently only FCSR (#31) is implemented. diff --git a/test/cctest/test-macro-assembler-mips.cc b/test/cctest/test-macro-assembler-mips.cc index 22718aed04..77cdaec72a 100644 --- a/test/cctest/test-macro-assembler-mips.cc +++ b/test/cctest/test-macro-assembler-mips.cc @@ -532,7 +532,7 @@ TEST(cvt_s_w_Trunc_uw_s) { uint32_t input = *i; auto fn = [](MacroAssembler* masm) { __ cvt_s_w(f0, f4); - __ Trunc_uw_s(f2, f0, f1); + __ Trunc_uw_s(f2, f0, f6); }; CHECK_EQ(static_cast(input), run_Cvt(input, fn)); }