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[wasm-simd][ia32] Prototype i64x2.bitmask

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Bug: v8:10997
Change-Id: I77e3fceec342698e25c8653b6a3dabe0ddbdc045
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2557057
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71472}
This commit is contained in:
Zhi An Ng 2020-11-30 02:20:01 +00:00 committed by Commit Bot
parent 3a4781c7ff
commit cd6d819114
11 changed files with 31 additions and 3 deletions
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8
src/codegen/ia32/assembler-ia32.cc
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@ -2999,6 +2999,14 @@ void Assembler::vroundpd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
EMIT(static_cast<byte>(mode) | 0x8); // Mask precision exception.
}
void Assembler::vmovmskpd(Register dst, XMMRegister src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(xmm0, kL128, k66, k0F, kWIG);
EMIT(0x50);
emit_sse_operand(dst, src);
}
void Assembler::vmovmskps(Register dst, XMMRegister src) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);

1
src/codegen/ia32/assembler-ia32.h
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@ -1484,6 +1484,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
vinstr(0x7E, src, xmm0, dst, k66, k0F, kWIG);
}
void vmovmskpd(Register dst, XMMRegister src);
void vmovmskps(Register dst, XMMRegister src);
void vpmovmskb(Register dst, XMMRegister src);

1
src/codegen/ia32/macro-assembler-ia32.h
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@ -311,6 +311,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP2_WITH_TYPE(Movapd, movapd, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Movupd, movupd, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Pmovmskb, pmovmskb, Register, XMMRegister)
AVX_OP2_WITH_TYPE(Movmskpd, movmskpd, Register, XMMRegister)
AVX_OP2_WITH_TYPE(Movmskps, movmskps, Register, XMMRegister)
#undef AVX_OP2_WITH_TYPE

4
src/compiler/backend/ia32/code-generator-ia32.cc
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@ -2142,6 +2142,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_SIMD_SHIFT(Psrlq, 6);
break;
}
case kIA32I64x2BitMask: {
__ Movmskpd(i.OutputRegister(), i.InputSimd128Register(0));
break;
}
case kSSEF32x4Splat: {
DCHECK_EQ(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
XMMRegister dst = i.OutputSimd128Register();

1
src/compiler/backend/ia32/instruction-codes-ia32.h
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@ -148,6 +148,7 @@ namespace compiler {
V(IA32I64x2Sub) \
V(IA32I64x2Mul) \
V(IA32I64x2ShrU) \
V(IA32I64x2BitMask) \
V(SSEF32x4Splat) \
V(AVXF32x4Splat) \
V(SSEF32x4ExtractLane) \

1
src/compiler/backend/ia32/instruction-scheduler-ia32.cc
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@ -127,6 +127,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kIA32I64x2Sub:
case kIA32I64x2Mul:
case kIA32I64x2ShrU:
case kIA32I64x2BitMask:
case kSSEF32x4Splat:
case kAVXF32x4Splat:
case kSSEF32x4ExtractLane:

1
src/compiler/backend/ia32/instruction-selector-ia32.cc
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@ -2180,6 +2180,7 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
V(F32x4SConvertI32x4) \
V(F32x4RecipApprox) \
V(F32x4RecipSqrtApprox) \
V(I64x2BitMask) \
V(I32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High) \
V(I32x4Neg) \

4
src/compiler/backend/instruction-selector.cc
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@ -2823,10 +2823,12 @@ void InstructionSelector::VisitI32x4SignSelect(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2SignSelect(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM && \
!V8_TARGET_ARCH_IA32
// TODO(v8:10997) Prototype i64x2.bitmask.
void InstructionSelector::VisitI64x2BitMask(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM
// && !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }

5
src/diagnostics/ia32/disasm-ia32.cc
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@ -1218,6 +1218,11 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
AppendToBuffer("vmovapd %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x50:
AppendToBuffer("vmovmskpd %s,%s", NameOfCPURegister(regop),
NameOfXMMRegister(rm));
current++;
break;
case 0x54:
AppendToBuffer("vandpd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));

2
test/cctest/test-disasm-ia32.cc
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@ -550,6 +550,7 @@ TEST(DisasmIa320) {
__ pinsrw(xmm5, edx, 5);
__ pinsrw(xmm5, Operand(edx, 4), 5);
__ movmskpd(edx, xmm5);
__ movmskps(edx, xmm5);
__ pmovmskb(edx, xmm5);
@ -796,6 +797,7 @@ TEST(DisasmIa320) {
__ vmovd(eax, xmm1);
__ vmovd(Operand(ebx, ecx, times_4, 10000), xmm1);
__ vmovmskpd(edx, xmm5);
__ vmovmskps(edx, xmm5);
__ vpmovmskb(ebx, xmm1);

6
test/cctest/wasm/test-run-wasm-simd.cc
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@ -1630,7 +1630,8 @@ WASM_SIMD_TEST(I32x4BitMask) {
}
// TODO(v8:10997) Prototyping i64x2.bitmask.
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM || \
V8_TARGET_ARCH_IA32
WASM_SIMD_TEST_NO_LOWERING(I64x2BitMask) {
FLAG_SCOPE(wasm_simd_post_mvp);
WasmRunner<int32_t, int64_t> r(execution_tier, lower_simd);
@ -1648,7 +1649,8 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2BitMask) {
CHECK_EQ(actual, expected);
}
}
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM ||
// V8_TARGET_ARCH_IA32
WASM_SIMD_TEST(I8x16Splat) {
WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);