AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Remove CodeAssembler::LoadRootsPointer

Browse Source 
This reverts two commits:

Introduce CodeAssembler::LoadRootsPointer
377803f804

[turbofan][x64] Reduce reg-to-reg moving instruction for
LoadRootsRegister IR
d4177d1173

LoadRootsPointer was used by indirections for heap constants and
external references from within CSA. Now that handling has moved to
the macro-assembler, it can be removed.

Bug: v8:6666
Change-Id: I868fe100e65a0a7a44ffc81674fa1ce79a56f7ed
Reviewed-on: https://chromium-review.googlesource.com/1097080
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#53770}
This commit is contained in:
jgruber 2018-06-15 16:34:54 +02:00 committed by Commit Bot
parent 4363a69335
commit cf00d6f06f
21 changed files with 0 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/compiler/arm/code-generator-arm.cc
View File

@ -917,10 +917,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mov(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ mov(i.OutputRegister(), kRootRegister);
DCHECK_EQ(LeaveCC, i.OutputSBit());
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

3
src/compiler/arm64/code-generator-arm64.cc
View File

@ -830,9 +830,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mov(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ mov(i.OutputRegister(), kRootRegister);
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

5
src/compiler/code-assembler.cc
View File

@ -472,11 +472,6 @@ Node* CodeAssembler::LoadParentFramePointer() {
return raw_assembler()->LoadParentFramePointer();
}
// TODO(jgruber): This can be removed.
TNode<IntPtrT> CodeAssembler::LoadRootsPointer() {
return UncheckedCast<IntPtrT>(raw_assembler()->LoadRootsPointer());
}
Node* CodeAssembler::LoadStackPointer() {
return raw_assembler()->LoadStackPointer();
}

3
src/compiler/code-assembler.h
View File

@ -770,9 +770,6 @@ class V8_EXPORT_PRIVATE CodeAssembler {
Node* LoadFramePointer();
Node* LoadParentFramePointer();
// Access to the roots pointer.
TNode<IntPtrT> LoadRootsPointer();
// Access to the stack pointer
Node* LoadStackPointer();

3
src/compiler/ia32/code-generator-ia32.cc
View File

@ -832,9 +832,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mov(i.OutputRegister(), ebp);
}
break;
case kArchRootsPointer:
// TODO(jgruber,v8:6666): Implement ia32 support.
UNREACHABLE();
case kArchTruncateDoubleToI: {
auto result = i.OutputRegister();
auto input = i.InputDoubleRegister(0);

1
src/compiler/instruction-codes.h
View File

@ -66,7 +66,6 @@ enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny };
V(ArchStackPointer) \
V(ArchFramePointer) \
V(ArchParentFramePointer) \
V(ArchRootsPointer) \
V(ArchTruncateDoubleToI) \
V(ArchStoreWithWriteBarrier) \
V(ArchStackSlot) \

1
src/compiler/instruction-scheduler.cc
View File

@ -248,7 +248,6 @@ int InstructionScheduler::GetInstructionFlags(const Instruction* instr) const {
case kArchNop:
case kArchFramePointer:
case kArchParentFramePointer:
case kArchRootsPointer:
case kArchStackSlot: // Despite its name this opcode will produce a
// reference to a frame slot, so it is not affected
// by the arm64 dual stack issues mentioned below.

7
src/compiler/instruction-selector.cc
View File

@ -1662,8 +1662,6 @@ void InstructionSelector::VisitNode(Node* node) {
return VisitLoadFramePointer(node);
case IrOpcode::kLoadParentFramePointer:
return VisitLoadParentFramePointer(node);
case IrOpcode::kLoadRootsPointer:
return VisitLoadRootsPointer(node);
case IrOpcode::kUnalignedLoad: {
LoadRepresentation type = LoadRepresentationOf(node->op());
MarkAsRepresentation(type.representation(), node);
@ -2028,11 +2026,6 @@ void InstructionSelector::VisitLoadParentFramePointer(Node* node) {
Emit(kArchParentFramePointer, g.DefineAsRegister(node));
}
void InstructionSelector::VisitLoadRootsPointer(Node* node) {
OperandGenerator g(this);
Emit(kArchRootsPointer, g.DefineAsRegister(node));
}
void InstructionSelector::VisitFloat64Acos(Node* node) {
VisitFloat64Ieee754Unop(node, kIeee754Float64Acos);
}

1
src/compiler/machine-graph-verifier.cc
View File

@ -120,7 +120,6 @@ class MachineRepresentationInferrer {
case IrOpcode::kLoadStackPointer:
case IrOpcode::kLoadFramePointer:
case IrOpcode::kLoadParentFramePointer:
case IrOpcode::kLoadRootsPointer:
representation_vector_[node->id()] =
MachineType::PointerRepresentation();
break;

1
src/compiler/machine-operator.cc
View File

@ -226,7 +226,6 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(LoadStackPointer, Operator::kNoProperties, 0, 0, 1) \
V(LoadFramePointer, Operator::kNoProperties, 0, 0, 1) \
V(LoadParentFramePointer, Operator::kNoProperties, 0, 0, 1) \
V(LoadRootsPointer, Operator::kNoProperties, 0, 0, 1) \
V(Int32PairAdd, Operator::kNoProperties, 4, 0, 2) \
V(Int32PairSub, Operator::kNoProperties, 4, 0, 2) \
V(Int32PairMul, Operator::kNoProperties, 4, 0, 2) \

3
src/compiler/machine-operator.h
View File

@ -614,9 +614,6 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* LoadFramePointer();
const Operator* LoadParentFramePointer();
// Access to the root register.
const Operator* LoadRootsPointer();
// atomic-load [base + index]
const Operator* Word32AtomicLoad(LoadRepresentation rep);
// atomic-load [base + index]

3
src/compiler/mips/code-generator-mips.cc
View File

@ -808,9 +808,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mov(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ mov(i.OutputRegister(), kRootRegister);
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

3
src/compiler/mips64/code-generator-mips64.cc
View File

@ -828,9 +828,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mov(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ mov(i.OutputRegister(), kRootRegister);
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

2
src/compiler/mips64/instruction-scheduler-mips64.cc
View File

@ -1249,8 +1249,6 @@ int InstructionScheduler::GetInstructionLatency(const Instruction* instr) {
case kArchParentFramePointer:
// Estimated max.
return AlignedMemoryLatency();
case kArchRootsPointer:
return 1;
case kArchTruncateDoubleToI:
return TruncateDoubleToIDelayedLatency();
case kArchStoreWithWriteBarrier:

1
src/compiler/opcodes.h
View File

@ -624,7 +624,6 @@
V(LoadStackPointer) \
V(LoadFramePointer) \
V(LoadParentFramePointer) \
V(LoadRootsPointer) \
V(UnalignedLoad) \
V(UnalignedStore) \
V(Int32PairAdd) \

4
src/compiler/ppc/code-generator-ppc.cc
View File

@ -1150,10 +1150,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mr(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ mr(i.OutputRegister(), kRootRegister);
DCHECK_EQ(LeaveRC, i.OutputRCBit());
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

3
src/compiler/raw-machine-assembler.h
View File

@ -741,9 +741,6 @@ class V8_EXPORT_PRIVATE RawMachineAssembler {
return AddNode(machine()->LoadParentFramePointer());
}
// Root pointer operations.
Node* LoadRootsPointer() { return AddNode(machine()->LoadRootsPointer()); }
// Parameters.
Node* Parameter(size_t index);

3
src/compiler/s390/code-generator-s390.cc
View File

@ -1572,9 +1572,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ LoadRR(i.OutputRegister(), fp);
}
break;
case kArchRootsPointer:
__ LoadRR(i.OutputRegister(), kRootRegister);
break;
case kArchTruncateDoubleToI:
__ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(),
i.InputDoubleRegister(0), DetermineStubCallMode());

1
src/compiler/verifier.cc
View File

@ -1711,7 +1711,6 @@ void Verifier::Visitor::Check(Node* node, const AllNodes& all) {
case IrOpcode::kLoadStackPointer:
case IrOpcode::kLoadFramePointer:
case IrOpcode::kLoadParentFramePointer:
case IrOpcode::kLoadRootsPointer:
case IrOpcode::kUnalignedLoad:
case IrOpcode::kUnalignedStore:
case IrOpcode::kWord32AtomicLoad:

3
src/compiler/x64/code-generator-x64.cc
View File

@ -926,9 +926,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ movq(i.OutputRegister(), rbp);
}
break;
case kArchRootsPointer:
__ movq(i.OutputRegister(), kRootRegister);
break;
case kArchTruncateDoubleToI: {
auto result = i.OutputRegister();
auto input = i.InputDoubleRegister(0);

11
src/compiler/x64/instruction-selector-x64.cc
View File

@ -178,17 +178,6 @@ class X64OperandGenerator final : public OperandGenerator {
}
}
}
if (operand->InputCount() == 2) {
Node* left = operand->InputAt(0);
Node* right = operand->InputAt(1);
if (left->opcode() == IrOpcode::kLoadRootsPointer &&
right->opcode() == IrOpcode::kInt64Constant) {
int64_t offset = OpParameter<int64_t>(right->op());
DCHECK(is_int32(offset));
inputs[(*input_count)++] = TempImmediate(static_cast<int32_t>(offset));
return kMode_Root;
}
}
BaseWithIndexAndDisplacement64Matcher m(operand, AddressOption::kAllowAll);
DCHECK(m.matches());
if (m.displacement() == nullptr || CanBeImmediate(m.displacement())) {