ARM64: Fix and improve --trace-sim register trace.
- Use standard names (except that our GREY is the standard BLACK). - Make non-bold colours explicit, otherwise the boldness can carry over into subsequent colour declarations. - I've moved some colours around to make them consistent. Register value updates (which are very common) now stand out less than they did, making the less-common (and arguably more important) debug announcements appear brighter. - FP registers and values are now magenta. - Integer registers and values are now cyan. - Memory accesses are now blue. - LOG_WRITE prints the source register for stores. - Loads are logged with a format similar to that used for stores. Specifically, the memory address is printed alongside the new register value. - Updates to D registers print the raw bits as well as the double value. Updates to S registers print the raw bits as well as the float value. (Previously, we printed both double and float interpretations of the bits, which was a bit cluttered.) BUG= R=ulan@chromium.org Review URL: https://codereview.chromium.org/548473002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23732 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
Jacob.Bramley@arm.com
parent
051972d240
commit
d0054c755f
@ -1517,7 +1517,9 @@ int Disassembler::SubstituteLiteralField(Instruction* instr,
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case LDR_w_lit:
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case LDR_x_lit:
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case LDR_s_lit:
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case LDR_d_lit: AppendToOutput("(addr %p)", instr->LiteralAddress()); break;
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case LDR_d_lit:
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AppendToOutput("(addr 0x%016" PRIxPTR ")", instr->LiteralAddress());
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break;
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default: UNREACHABLE();
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}
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@ -352,9 +352,9 @@ class Instruction {
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// Patch a literal load instruction to load from 'source'.
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void SetImmLLiteral(Instruction* source);
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uint8_t* LiteralAddress() {
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uintptr_t LiteralAddress() {
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int offset = ImmLLiteral() << kLoadLiteralScaleLog2;
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return reinterpret_cast<uint8_t*>(this) + offset;
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return reinterpret_cast<uintptr_t>(this) + offset;
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}
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enum CheckAlignment { NO_CHECK, CHECK_ALIGNMENT };
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@ -30,30 +30,28 @@ namespace internal {
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// Helpers for colors.
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// Depending on your terminal configuration, the colour names may not match the
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// observed colours.
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#define COLOUR(colour_code) "\033[" colour_code "m"
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#define BOLD(colour_code) "1;" colour_code
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#define NORMAL ""
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#define GREY "30"
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#define GREEN "32"
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#define ORANGE "33"
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#define BLUE "34"
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#define PURPLE "35"
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#define INDIGO "36"
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#define WHITE "37"
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#define COLOUR(colour_code) "\033[0;" colour_code "m"
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#define COLOUR_BOLD(colour_code) "\033[1;" colour_code "m"
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#define NORMAL ""
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#define GREY "30"
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#define RED "31"
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#define GREEN "32"
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#define YELLOW "33"
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#define BLUE "34"
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#define MAGENTA "35"
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#define CYAN "36"
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#define WHITE "37"
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typedef char const * const TEXT_COLOUR;
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TEXT_COLOUR clr_normal = FLAG_log_colour ? COLOUR(NORMAL) : "";
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TEXT_COLOUR clr_flag_name = FLAG_log_colour ? COLOUR(BOLD(GREY)) : "";
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TEXT_COLOUR clr_flag_value = FLAG_log_colour ? COLOUR(BOLD(WHITE)) : "";
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TEXT_COLOUR clr_reg_name = FLAG_log_colour ? COLOUR(BOLD(BLUE)) : "";
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TEXT_COLOUR clr_reg_value = FLAG_log_colour ? COLOUR(BOLD(INDIGO)) : "";
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TEXT_COLOUR clr_fpreg_name = FLAG_log_colour ? COLOUR(BOLD(ORANGE)) : "";
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TEXT_COLOUR clr_fpreg_value = FLAG_log_colour ? COLOUR(BOLD(PURPLE)) : "";
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TEXT_COLOUR clr_memory_value = FLAG_log_colour ? COLOUR(BOLD(GREEN)) : "";
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TEXT_COLOUR clr_memory_address = FLAG_log_colour ? COLOUR(GREEN) : "";
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TEXT_COLOUR clr_debug_number = FLAG_log_colour ? COLOUR(BOLD(ORANGE)) : "";
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TEXT_COLOUR clr_debug_message = FLAG_log_colour ? COLOUR(ORANGE) : "";
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TEXT_COLOUR clr_flag_name = FLAG_log_colour ? COLOUR_BOLD(WHITE) : "";
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TEXT_COLOUR clr_flag_value = FLAG_log_colour ? COLOUR(NORMAL) : "";
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TEXT_COLOUR clr_reg_name = FLAG_log_colour ? COLOUR_BOLD(CYAN) : "";
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TEXT_COLOUR clr_reg_value = FLAG_log_colour ? COLOUR(CYAN) : "";
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TEXT_COLOUR clr_fpreg_name = FLAG_log_colour ? COLOUR_BOLD(MAGENTA) : "";
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TEXT_COLOUR clr_fpreg_value = FLAG_log_colour ? COLOUR(MAGENTA) : "";
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TEXT_COLOUR clr_memory_address = FLAG_log_colour ? COLOUR_BOLD(BLUE) : "";
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TEXT_COLOUR clr_debug_number = FLAG_log_colour ? COLOUR_BOLD(YELLOW) : "";
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TEXT_COLOUR clr_debug_message = FLAG_log_colour ? COLOUR(YELLOW) : "";
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TEXT_COLOUR clr_printf = FLAG_log_colour ? COLOUR(GREEN) : "";
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@ -337,7 +335,7 @@ uintptr_t Simulator::PopAddress() {
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uintptr_t Simulator::StackLimit() const {
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// Leave a safety margin of 1024 bytes to prevent overrunning the stack when
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// pushing values.
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return reinterpret_cast<uintptr_t>(stack_limit_) + 1024;
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return stack_limit_ + 1024;
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}
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@ -380,11 +378,11 @@ void Simulator::Init(FILE* stream) {
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// Allocate and setup the simulator stack.
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stack_size_ = (FLAG_sim_stack_size * KB) + (2 * stack_protection_size_);
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stack_ = new byte[stack_size_];
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stack_ = reinterpret_cast<uintptr_t>(new byte[stack_size_]);
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stack_limit_ = stack_ + stack_protection_size_;
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byte* tos = stack_ + stack_size_ - stack_protection_size_;
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// The stack pointer must be 16 bytes aligned.
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set_sp(reinterpret_cast<int64_t>(tos) & ~0xfUL);
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uintptr_t tos = stack_ + stack_size_ - stack_protection_size_;
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// The stack pointer must be 16-byte aligned.
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set_sp(tos & ~0xfUL);
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stream_ = stream;
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print_disasm_ = new PrintDisassembler(stream_);
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@ -420,7 +418,7 @@ void Simulator::ResetState() {
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Simulator::~Simulator() {
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delete[] stack_;
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delete[] reinterpret_cast<byte*>(stack_);
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if (FLAG_log_instruction_stats) {
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delete instrument_;
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}
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@ -734,15 +732,15 @@ void* Simulator::RedirectExternalReference(void* external_function,
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const char* Simulator::xreg_names[] = {
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"ip0", "ip1", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "cp", "jssp", "fp", "lr", "xzr", "csp"};
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"ip0", "ip1", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "cp", "jssp", "fp", "lr", "xzr", "csp"};
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const char* Simulator::wreg_names[] = {
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"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
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"w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
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"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
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"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
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"w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
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"w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
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"w24", "w25", "w26", "wcp", "wjssp", "wfp", "wlr", "wzr", "wcsp"};
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const char* Simulator::sreg_names[] = {
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@ -765,40 +763,47 @@ const char* Simulator::vreg_names[] = {
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const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
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STATIC_ASSERT(arraysize(Simulator::wreg_names) == (kNumberOfRegisters + 1));
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DCHECK(code < kNumberOfRegisters);
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// If the code represents the stack pointer, index the name after zr.
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if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
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code = kZeroRegCode + 1;
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}
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return wreg_names[code];
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// Using basic pointer arithmetic (instead of an array index) avoids an
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// erroneous GCC warning about an out-of-bounds array index.
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return *(wreg_names + code);
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}
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const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
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STATIC_ASSERT(arraysize(Simulator::xreg_names) == (kNumberOfRegisters + 1));
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DCHECK(code < kNumberOfRegisters);
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// If the code represents the stack pointer, index the name after zr.
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if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
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code = kZeroRegCode + 1;
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}
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return xreg_names[code];
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return *(xreg_names + code);
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}
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const char* Simulator::SRegNameForCode(unsigned code) {
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STATIC_ASSERT(arraysize(Simulator::sreg_names) == kNumberOfFPRegisters);
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DCHECK(code < kNumberOfFPRegisters);
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return sreg_names[code];
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return *(sreg_names + code);
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}
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const char* Simulator::DRegNameForCode(unsigned code) {
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STATIC_ASSERT(arraysize(Simulator::dreg_names) == kNumberOfFPRegisters);
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DCHECK(code < kNumberOfFPRegisters);
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return dreg_names[code];
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return *(dreg_names + code);
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}
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const char* Simulator::VRegNameForCode(unsigned code) {
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STATIC_ASSERT(arraysize(Simulator::vreg_names) == kNumberOfFPRegisters);
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DCHECK(code < kNumberOfFPRegisters);
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return vreg_names[code];
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return *(vreg_names + code);
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}
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@ -855,6 +860,7 @@ T Simulator::AddWithCarry(bool set_flags,
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nzcv().SetZ(Z);
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nzcv().SetC(C);
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nzcv().SetV(V);
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LogSystemRegister(NZCV);
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}
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return result;
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}
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@ -978,6 +984,7 @@ void Simulator::FPCompare(double val0, double val1) {
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} else {
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UNREACHABLE();
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}
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LogSystemRegister(NZCV);
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}
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@ -1044,117 +1051,206 @@ void Simulator::PrintInstructionsAt(Instruction* start, uint64_t count) {
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}
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void Simulator::PrintSystemRegisters(bool print_all) {
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static bool first_run = true;
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static SimSystemRegister last_nzcv;
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if (print_all || first_run || (last_nzcv.RawValue() != nzcv().RawValue())) {
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fprintf(stream_, "# %sFLAGS: %sN:%d Z:%d C:%d V:%d%s\n",
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clr_flag_name,
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clr_flag_value,
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nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
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clr_normal);
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}
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last_nzcv = nzcv();
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static SimSystemRegister last_fpcr;
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if (print_all || first_run || (last_fpcr.RawValue() != fpcr().RawValue())) {
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static const char * rmode[] = {
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"0b00 (Round to Nearest)",
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"0b01 (Round towards Plus Infinity)",
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"0b10 (Round towards Minus Infinity)",
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"0b11 (Round towards Zero)"
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};
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DCHECK(fpcr().RMode() < arraysize(rmode));
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fprintf(stream_, "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
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clr_flag_name,
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clr_flag_value,
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fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
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clr_normal);
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}
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last_fpcr = fpcr();
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first_run = false;
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void Simulator::PrintSystemRegisters() {
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PrintSystemRegister(NZCV);
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PrintSystemRegister(FPCR);
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}
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void Simulator::PrintRegisters(bool print_all_regs) {
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static bool first_run = true;
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static int64_t last_regs[kNumberOfRegisters];
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void Simulator::PrintRegisters() {
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for (unsigned i = 0; i < kNumberOfRegisters; i++) {
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if (print_all_regs || first_run ||
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(last_regs[i] != xreg(i, Reg31IsStackPointer))) {
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fprintf(stream_,
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"# %s%4s:%s 0x%016" PRIx64 "%s\n",
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clr_reg_name,
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XRegNameForCode(i, Reg31IsStackPointer),
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clr_reg_value,
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xreg(i, Reg31IsStackPointer),
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clr_normal);
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}
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// Cache the new register value so the next run can detect any changes.
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last_regs[i] = xreg(i, Reg31IsStackPointer);
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PrintRegister(i);
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}
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first_run = false;
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}
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void Simulator::PrintFPRegisters(bool print_all_regs) {
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static bool first_run = true;
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static uint64_t last_regs[kNumberOfFPRegisters];
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// Print as many rows of registers as necessary, keeping each individual
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// register in the same column each time (to make it easy to visually scan
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// for changes).
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void Simulator::PrintFPRegisters() {
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for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
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if (print_all_regs || first_run || (last_regs[i] != dreg_bits(i))) {
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fprintf(stream_,
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"# %s %4s:%s 0x%016" PRIx64 "%s (%s%s:%s %g%s %s:%s %g%s)\n",
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clr_fpreg_name,
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VRegNameForCode(i),
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clr_fpreg_value,
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dreg_bits(i),
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clr_normal,
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clr_fpreg_name,
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DRegNameForCode(i),
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clr_fpreg_value,
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dreg(i),
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clr_fpreg_name,
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SRegNameForCode(i),
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clr_fpreg_value,
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sreg(i),
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clr_normal);
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}
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// Cache the new register value so the next run can detect any changes.
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last_regs[i] = dreg_bits(i);
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PrintFPRegister(i);
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}
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first_run = false;
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}
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void Simulator::PrintProcessorState() {
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PrintSystemRegisters();
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PrintRegisters();
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PrintFPRegisters();
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void Simulator::PrintRegister(unsigned code, Reg31Mode r31mode) {
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// Don't print writes into xzr.
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if ((code == kZeroRegCode) && (r31mode == Reg31IsZeroRegister)) {
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return;
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}
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// The template is "# x<code>:value".
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fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s\n",
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clr_reg_name, XRegNameForCode(code, r31mode),
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clr_reg_value, reg<uint64_t>(code, r31mode), clr_normal);
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}
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void Simulator::PrintWrite(uintptr_t address, uint64_t value,
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unsigned num_bytes) {
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// The template is "# value -> address". The format string is not used
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// directly in the printf because some compilers struggle with the
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// parametrized width field (%0*).
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const char* format = "# %s0x%0*" PRIx64 "%s -> %s0x%016" PRIxPTR "%s\n";
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fprintf(stream_,
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format,
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clr_memory_value,
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num_bytes * 2, // The width in hexadecimal characters.
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value,
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clr_normal,
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clr_memory_address,
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address,
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clr_normal);
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void Simulator::PrintFPRegister(unsigned code, PrintFPRegisterSizes sizes) {
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// The template is "# v<code>:bits (d<code>:value, ...)".
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DCHECK(sizes != 0);
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DCHECK((sizes & kPrintAllFPRegValues) == sizes);
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// Print the raw bits.
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fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (",
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clr_fpreg_name, VRegNameForCode(code),
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clr_fpreg_value, fpreg<uint64_t>(code), clr_normal);
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// Print all requested value interpretations.
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bool need_separator = false;
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if (sizes & kPrintDRegValue) {
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fprintf(stream_, "%s%s%s: %s%g%s",
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need_separator ? ", " : "",
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clr_fpreg_name, DRegNameForCode(code),
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clr_fpreg_value, fpreg<double>(code), clr_normal);
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need_separator = true;
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}
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if (sizes & kPrintSRegValue) {
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fprintf(stream_, "%s%s%s: %s%g%s",
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need_separator ? ", " : "",
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clr_fpreg_name, SRegNameForCode(code),
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clr_fpreg_value, fpreg<float>(code), clr_normal);
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need_separator = true;
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}
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// End the value list.
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fprintf(stream_, ")\n");
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}
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void Simulator::PrintSystemRegister(SystemRegister id) {
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switch (id) {
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case NZCV:
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fprintf(stream_, "# %sNZCV: %sN:%d Z:%d C:%d V:%d%s\n",
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clr_flag_name, clr_flag_value,
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nzcv().N(), nzcv().Z(), nzcv().C(), nzcv().V(),
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clr_normal);
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break;
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case FPCR: {
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static const char * rmode[] = {
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"0b00 (Round to Nearest)",
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"0b01 (Round towards Plus Infinity)",
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"0b10 (Round towards Minus Infinity)",
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"0b11 (Round towards Zero)"
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};
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DCHECK(fpcr().RMode() < arraysize(rmode));
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fprintf(stream_,
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"# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
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clr_flag_name, clr_flag_value,
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fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
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clr_normal);
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break;
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}
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default:
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UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Simulator::PrintRead(uintptr_t address,
|
||||
size_t size,
|
||||
unsigned reg_code) {
|
||||
USE(size); // Size is unused here.
|
||||
|
||||
// The template is "# x<code>:value <- address".
|
||||
fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s",
|
||||
clr_reg_name, XRegNameForCode(reg_code),
|
||||
clr_reg_value, reg<uint64_t>(reg_code), clr_normal);
|
||||
|
||||
fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
|
||||
clr_memory_address, address, clr_normal);
|
||||
}
|
||||
|
||||
|
||||
void Simulator::PrintReadFP(uintptr_t address,
|
||||
size_t size,
|
||||
unsigned reg_code) {
|
||||
// The template is "# reg:bits (reg:value) <- address".
|
||||
switch (size) {
|
||||
case kSRegSize:
|
||||
fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%gf%s)",
|
||||
clr_fpreg_name, VRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
|
||||
clr_fpreg_name, SRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<float>(reg_code), clr_normal);
|
||||
break;
|
||||
case kDRegSize:
|
||||
fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%g%s)",
|
||||
clr_fpreg_name, VRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
|
||||
clr_fpreg_name, DRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<double>(reg_code), clr_normal);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
fprintf(stream_, " <- %s0x%016" PRIxPTR "%s\n",
|
||||
clr_memory_address, address, clr_normal);
|
||||
}
|
||||
|
||||
|
||||
void Simulator::PrintWrite(uintptr_t address,
|
||||
size_t size,
|
||||
unsigned reg_code) {
|
||||
// The template is "# reg:value -> address". To keep the trace tidy and
|
||||
// readable, the value is aligned with the values in the register trace.
|
||||
switch (size) {
|
||||
case kByteSizeInBytes:
|
||||
fprintf(stream_, "# %s%5s<7:0>: %s0x%02" PRIx8 "%s",
|
||||
clr_reg_name, WRegNameForCode(reg_code),
|
||||
clr_reg_value, reg<uint8_t>(reg_code), clr_normal);
|
||||
break;
|
||||
case kHalfWordSizeInBytes:
|
||||
fprintf(stream_, "# %s%5s<15:0>: %s0x%04" PRIx16 "%s",
|
||||
clr_reg_name, WRegNameForCode(reg_code),
|
||||
clr_reg_value, reg<uint16_t>(reg_code), clr_normal);
|
||||
break;
|
||||
case kWRegSize:
|
||||
fprintf(stream_, "# %s%5s: %s0x%08" PRIx32 "%s",
|
||||
clr_reg_name, WRegNameForCode(reg_code),
|
||||
clr_reg_value, reg<uint32_t>(reg_code), clr_normal);
|
||||
break;
|
||||
case kXRegSize:
|
||||
fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s",
|
||||
clr_reg_name, XRegNameForCode(reg_code),
|
||||
clr_reg_value, reg<uint64_t>(reg_code), clr_normal);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
|
||||
clr_memory_address, address, clr_normal);
|
||||
}
|
||||
|
||||
|
||||
void Simulator::PrintWriteFP(uintptr_t address,
|
||||
size_t size,
|
||||
unsigned reg_code) {
|
||||
// The template is "# reg:bits (reg:value) -> address". To keep the trace tidy
|
||||
// and readable, the value is aligned with the values in the register trace.
|
||||
switch (size) {
|
||||
case kSRegSize:
|
||||
fprintf(stream_, "# %s%5s<31:0>: %s0x%08" PRIx32 "%s (%s%s: %s%gf%s)",
|
||||
clr_fpreg_name, VRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<uint32_t>(reg_code), clr_normal,
|
||||
clr_fpreg_name, SRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<float>(reg_code), clr_normal);
|
||||
break;
|
||||
case kDRegSize:
|
||||
fprintf(stream_, "# %s%5s: %s0x%016" PRIx64 "%s (%s%s: %s%g%s)",
|
||||
clr_fpreg_name, VRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<uint64_t>(reg_code), clr_normal,
|
||||
clr_fpreg_name, DRegNameForCode(reg_code),
|
||||
clr_fpreg_value, fpreg<double>(reg_code), clr_normal);
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
fprintf(stream_, " -> %s0x%016" PRIxPTR "%s\n",
|
||||
clr_memory_address, address, clr_normal);
|
||||
}
|
||||
|
||||
|
||||
@ -1383,6 +1479,7 @@ void Simulator::LogicalHelper(Instruction* instr, T op2) {
|
||||
nzcv().SetZ(CalcZFlag(result));
|
||||
nzcv().SetC(0);
|
||||
nzcv().SetV(0);
|
||||
LogSystemRegister(NZCV);
|
||||
}
|
||||
|
||||
set_reg<T>(instr->Rd(), result, instr->RdMode());
|
||||
@ -1423,6 +1520,7 @@ void Simulator::ConditionalCompareHelper(Instruction* instr, T op2) {
|
||||
} else {
|
||||
// If the condition fails, set the status flags to the nzcv immediate.
|
||||
nzcv().SetFlags(instr->Nzcv());
|
||||
LogSystemRegister(NZCV);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1463,8 +1561,8 @@ void Simulator::LoadStoreHelper(Instruction* instr,
|
||||
AddrMode addrmode) {
|
||||
unsigned srcdst = instr->Rt();
|
||||
unsigned addr_reg = instr->Rn();
|
||||
uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode);
|
||||
uint8_t* stack = NULL;
|
||||
uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
|
||||
uintptr_t stack = 0;
|
||||
|
||||
// Handle the writeback for stores before the store. On a CPU the writeback
|
||||
// and the store are atomic, but when running on the simulator it is possible
|
||||
@ -1478,22 +1576,24 @@ void Simulator::LoadStoreHelper(Instruction* instr,
|
||||
|
||||
// For store the address post writeback is used to check access below the
|
||||
// stack.
|
||||
stack = reinterpret_cast<uint8_t*>(sp());
|
||||
stack = sp();
|
||||
}
|
||||
|
||||
LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreOpMask));
|
||||
switch (op) {
|
||||
case LDRB_w: set_wreg(srcdst, MemoryRead<uint8_t>(address)); break;
|
||||
case LDRH_w: set_wreg(srcdst, MemoryRead<uint16_t>(address)); break;
|
||||
case LDR_w: set_wreg(srcdst, MemoryRead<uint32_t>(address)); break;
|
||||
case LDR_x: set_xreg(srcdst, MemoryRead<uint64_t>(address)); break;
|
||||
case LDRSB_w: set_wreg(srcdst, MemoryRead<int8_t>(address)); break;
|
||||
case LDRSH_w: set_wreg(srcdst, MemoryRead<int16_t>(address)); break;
|
||||
case LDRSB_x: set_xreg(srcdst, MemoryRead<int8_t>(address)); break;
|
||||
case LDRSH_x: set_xreg(srcdst, MemoryRead<int16_t>(address)); break;
|
||||
case LDRSW_x: set_xreg(srcdst, MemoryRead<int32_t>(address)); break;
|
||||
case LDR_s: set_sreg(srcdst, MemoryRead<float>(address)); break;
|
||||
case LDR_d: set_dreg(srcdst, MemoryRead<double>(address)); break;
|
||||
// Use _no_log variants to suppress the register trace (LOG_REGS,
|
||||
// LOG_FP_REGS). We will print a more detailed log.
|
||||
case LDRB_w: set_wreg_no_log(srcdst, MemoryRead<uint8_t>(address)); break;
|
||||
case LDRH_w: set_wreg_no_log(srcdst, MemoryRead<uint16_t>(address)); break;
|
||||
case LDR_w: set_wreg_no_log(srcdst, MemoryRead<uint32_t>(address)); break;
|
||||
case LDR_x: set_xreg_no_log(srcdst, MemoryRead<uint64_t>(address)); break;
|
||||
case LDRSB_w: set_wreg_no_log(srcdst, MemoryRead<int8_t>(address)); break;
|
||||
case LDRSH_w: set_wreg_no_log(srcdst, MemoryRead<int16_t>(address)); break;
|
||||
case LDRSB_x: set_xreg_no_log(srcdst, MemoryRead<int8_t>(address)); break;
|
||||
case LDRSH_x: set_xreg_no_log(srcdst, MemoryRead<int16_t>(address)); break;
|
||||
case LDRSW_x: set_xreg_no_log(srcdst, MemoryRead<int32_t>(address)); break;
|
||||
case LDR_s: set_sreg_no_log(srcdst, MemoryRead<float>(address)); break;
|
||||
case LDR_d: set_dreg_no_log(srcdst, MemoryRead<double>(address)); break;
|
||||
|
||||
case STRB_w: MemoryWrite<uint8_t>(address, wreg(srcdst)); break;
|
||||
case STRH_w: MemoryWrite<uint16_t>(address, wreg(srcdst)); break;
|
||||
@ -1505,6 +1605,23 @@ void Simulator::LoadStoreHelper(Instruction* instr,
|
||||
default: UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
// Print a detailed trace (including the memory address) instead of the basic
|
||||
// register:value trace generated by set_*reg().
|
||||
size_t access_size = 1 << instr->SizeLS();
|
||||
if (instr->IsLoad()) {
|
||||
if ((op == LDR_s) || (op == LDR_d)) {
|
||||
LogReadFP(address, access_size, srcdst);
|
||||
} else {
|
||||
LogRead(address, access_size, srcdst);
|
||||
}
|
||||
} else {
|
||||
if ((op == STR_s) || (op == STR_d)) {
|
||||
LogWriteFP(address, access_size, srcdst);
|
||||
} else {
|
||||
LogWrite(address, access_size, srcdst);
|
||||
}
|
||||
}
|
||||
|
||||
// Handle the writeback for loads after the load to ensure safe pop
|
||||
// operation even when interrupted in the middle of it. The stack pointer
|
||||
// is only updated after the load so pop(fp) will never break the invariant
|
||||
@ -1512,7 +1629,7 @@ void Simulator::LoadStoreHelper(Instruction* instr,
|
||||
if (instr->IsLoad()) {
|
||||
// For loads the address pre writeback is used to check access below the
|
||||
// stack.
|
||||
stack = reinterpret_cast<uint8_t*>(sp());
|
||||
stack = sp();
|
||||
|
||||
LoadStoreWriteBack(addr_reg, offset, addrmode);
|
||||
}
|
||||
@ -1548,9 +1665,11 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
|
||||
unsigned rt = instr->Rt();
|
||||
unsigned rt2 = instr->Rt2();
|
||||
unsigned addr_reg = instr->Rn();
|
||||
int offset = instr->ImmLSPair() << instr->SizeLSPair();
|
||||
uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode);
|
||||
uint8_t* stack = NULL;
|
||||
size_t access_size = 1 << instr->SizeLSPair();
|
||||
int64_t offset = instr->ImmLSPair() * access_size;
|
||||
uintptr_t address = LoadStoreAddress(addr_reg, offset, addrmode);
|
||||
uintptr_t address2 = address + access_size;
|
||||
uintptr_t stack = 0;
|
||||
|
||||
// Handle the writeback for stores before the store. On a CPU the writeback
|
||||
// and the store are atomic, but when running on the simulator it is possible
|
||||
@ -1564,7 +1683,7 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
|
||||
|
||||
// For store the address post writeback is used to check access below the
|
||||
// stack.
|
||||
stack = reinterpret_cast<uint8_t*>(sp());
|
||||
stack = sp();
|
||||
}
|
||||
|
||||
LoadStorePairOp op =
|
||||
@ -1574,54 +1693,85 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
|
||||
DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2));
|
||||
|
||||
switch (op) {
|
||||
// Use _no_log variants to suppress the register trace (LOG_REGS,
|
||||
// LOG_FP_REGS). We will print a more detailed log.
|
||||
case LDP_w: {
|
||||
set_wreg(rt, MemoryRead<uint32_t>(address));
|
||||
set_wreg(rt2, MemoryRead<uint32_t>(address + kWRegSize));
|
||||
DCHECK(access_size == kWRegSize);
|
||||
set_wreg_no_log(rt, MemoryRead<uint32_t>(address));
|
||||
set_wreg_no_log(rt2, MemoryRead<uint32_t>(address2));
|
||||
break;
|
||||
}
|
||||
case LDP_s: {
|
||||
set_sreg(rt, MemoryRead<float>(address));
|
||||
set_sreg(rt2, MemoryRead<float>(address + kSRegSize));
|
||||
DCHECK(access_size == kSRegSize);
|
||||
set_sreg_no_log(rt, MemoryRead<float>(address));
|
||||
set_sreg_no_log(rt2, MemoryRead<float>(address2));
|
||||
break;
|
||||
}
|
||||
case LDP_x: {
|
||||
set_xreg(rt, MemoryRead<uint64_t>(address));
|
||||
set_xreg(rt2, MemoryRead<uint64_t>(address + kXRegSize));
|
||||
DCHECK(access_size == kXRegSize);
|
||||
set_xreg_no_log(rt, MemoryRead<uint64_t>(address));
|
||||
set_xreg_no_log(rt2, MemoryRead<uint64_t>(address2));
|
||||
break;
|
||||
}
|
||||
case LDP_d: {
|
||||
set_dreg(rt, MemoryRead<double>(address));
|
||||
set_dreg(rt2, MemoryRead<double>(address + kDRegSize));
|
||||
DCHECK(access_size == kDRegSize);
|
||||
set_dreg_no_log(rt, MemoryRead<double>(address));
|
||||
set_dreg_no_log(rt2, MemoryRead<double>(address2));
|
||||
break;
|
||||
}
|
||||
case LDPSW_x: {
|
||||
set_xreg(rt, MemoryRead<int32_t>(address));
|
||||
set_xreg(rt2, MemoryRead<int32_t>(address + kWRegSize));
|
||||
DCHECK(access_size == kWRegSize);
|
||||
set_xreg_no_log(rt, MemoryRead<int32_t>(address));
|
||||
set_xreg_no_log(rt2, MemoryRead<int32_t>(address2));
|
||||
break;
|
||||
}
|
||||
case STP_w: {
|
||||
DCHECK(access_size == kWRegSize);
|
||||
MemoryWrite<uint32_t>(address, wreg(rt));
|
||||
MemoryWrite<uint32_t>(address + kWRegSize, wreg(rt2));
|
||||
MemoryWrite<uint32_t>(address2, wreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_s: {
|
||||
DCHECK(access_size == kSRegSize);
|
||||
MemoryWrite<float>(address, sreg(rt));
|
||||
MemoryWrite<float>(address + kSRegSize, sreg(rt2));
|
||||
MemoryWrite<float>(address2, sreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_x: {
|
||||
DCHECK(access_size == kXRegSize);
|
||||
MemoryWrite<uint64_t>(address, xreg(rt));
|
||||
MemoryWrite<uint64_t>(address + kXRegSize, xreg(rt2));
|
||||
MemoryWrite<uint64_t>(address2, xreg(rt2));
|
||||
break;
|
||||
}
|
||||
case STP_d: {
|
||||
DCHECK(access_size == kDRegSize);
|
||||
MemoryWrite<double>(address, dreg(rt));
|
||||
MemoryWrite<double>(address + kDRegSize, dreg(rt2));
|
||||
MemoryWrite<double>(address2, dreg(rt2));
|
||||
break;
|
||||
}
|
||||
default: UNREACHABLE();
|
||||
}
|
||||
|
||||
// Print a detailed trace (including the memory address) instead of the basic
|
||||
// register:value trace generated by set_*reg().
|
||||
if (instr->IsLoad()) {
|
||||
if ((op == LDP_s) || (op == LDP_d)) {
|
||||
LogReadFP(address, access_size, rt);
|
||||
LogReadFP(address2, access_size, rt2);
|
||||
} else {
|
||||
LogRead(address, access_size, rt);
|
||||
LogRead(address2, access_size, rt2);
|
||||
}
|
||||
} else {
|
||||
if ((op == STP_s) || (op == STP_d)) {
|
||||
LogWriteFP(address, access_size, rt);
|
||||
LogWriteFP(address2, access_size, rt2);
|
||||
} else {
|
||||
LogWrite(address, access_size, rt);
|
||||
LogWrite(address2, access_size, rt2);
|
||||
}
|
||||
}
|
||||
|
||||
// Handle the writeback for loads after the load to ensure safe pop
|
||||
// operation even when interrupted in the middle of it. The stack pointer
|
||||
// is only updated after the load so pop(fp) will never break the invariant
|
||||
@ -1629,7 +1779,7 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
|
||||
if (instr->IsLoad()) {
|
||||
// For loads the address pre writeback is used to check access below the
|
||||
// stack.
|
||||
stack = reinterpret_cast<uint8_t*>(sp());
|
||||
stack = sp();
|
||||
|
||||
LoadStoreWriteBack(addr_reg, offset, addrmode);
|
||||
}
|
||||
@ -1641,24 +1791,37 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
|
||||
|
||||
|
||||
void Simulator::VisitLoadLiteral(Instruction* instr) {
|
||||
uint8_t* address = instr->LiteralAddress();
|
||||
uintptr_t address = instr->LiteralAddress();
|
||||
unsigned rt = instr->Rt();
|
||||
|
||||
switch (instr->Mask(LoadLiteralMask)) {
|
||||
case LDR_w_lit: set_wreg(rt, MemoryRead<uint32_t>(address)); break;
|
||||
case LDR_x_lit: set_xreg(rt, MemoryRead<uint64_t>(address)); break;
|
||||
case LDR_s_lit: set_sreg(rt, MemoryRead<float>(address)); break;
|
||||
case LDR_d_lit: set_dreg(rt, MemoryRead<double>(address)); break;
|
||||
// Use _no_log variants to suppress the register trace (LOG_REGS,
|
||||
// LOG_FP_REGS), then print a more detailed log.
|
||||
case LDR_w_lit:
|
||||
set_wreg_no_log(rt, MemoryRead<uint32_t>(address));
|
||||
LogRead(address, kWRegSize, rt);
|
||||
break;
|
||||
case LDR_x_lit:
|
||||
set_xreg_no_log(rt, MemoryRead<uint64_t>(address));
|
||||
LogRead(address, kXRegSize, rt);
|
||||
break;
|
||||
case LDR_s_lit:
|
||||
set_sreg_no_log(rt, MemoryRead<float>(address));
|
||||
LogReadFP(address, kSRegSize, rt);
|
||||
break;
|
||||
case LDR_d_lit:
|
||||
set_dreg_no_log(rt, MemoryRead<double>(address));
|
||||
LogReadFP(address, kDRegSize, rt);
|
||||
break;
|
||||
default: UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint8_t* Simulator::LoadStoreAddress(unsigned addr_reg,
|
||||
int64_t offset,
|
||||
AddrMode addrmode) {
|
||||
uintptr_t Simulator::LoadStoreAddress(unsigned addr_reg, int64_t offset,
|
||||
AddrMode addrmode) {
|
||||
const unsigned kSPRegCode = kSPRegInternalCode & kRegCodeMask;
|
||||
int64_t address = xreg(addr_reg, Reg31IsStackPointer);
|
||||
uint64_t address = xreg(addr_reg, Reg31IsStackPointer);
|
||||
if ((addr_reg == kSPRegCode) && ((address % 16) != 0)) {
|
||||
// When the base register is SP the stack pointer is required to be
|
||||
// quadword aligned prior to the address calculation and write-backs.
|
||||
@ -1670,7 +1833,7 @@ uint8_t* Simulator::LoadStoreAddress(unsigned addr_reg,
|
||||
address += offset;
|
||||
}
|
||||
|
||||
return reinterpret_cast<uint8_t*>(address);
|
||||
return address;
|
||||
}
|
||||
|
||||
|
||||
@ -1685,12 +1848,12 @@ void Simulator::LoadStoreWriteBack(unsigned addr_reg,
|
||||
}
|
||||
|
||||
|
||||
void Simulator::CheckMemoryAccess(uint8_t* address, uint8_t* stack) {
|
||||
void Simulator::CheckMemoryAccess(uintptr_t address, uintptr_t stack) {
|
||||
if ((address >= stack_limit_) && (address < stack)) {
|
||||
fprintf(stream_, "ACCESS BELOW STACK POINTER:\n");
|
||||
fprintf(stream_, " sp is here: 0x%16p\n", stack);
|
||||
fprintf(stream_, " access was here: 0x%16p\n", address);
|
||||
fprintf(stream_, " stack limit is here: 0x%16p\n", stack_limit_);
|
||||
fprintf(stream_, " sp is here: 0x%016" PRIx64 "\n", stack);
|
||||
fprintf(stream_, " access was here: 0x%016" PRIx64 "\n", address);
|
||||
fprintf(stream_, " stack limit is here: 0x%016" PRIx64 "\n", stack_limit_);
|
||||
fprintf(stream_, "\n");
|
||||
FATAL("ACCESS BELOW STACK POINTER");
|
||||
}
|
||||
@ -2245,6 +2408,7 @@ void Simulator::VisitFPConditionalCompare(Instruction* instr) {
|
||||
} else {
|
||||
// If the condition fails, set the status flags to the nzcv immediate.
|
||||
nzcv().SetFlags(instr->Nzcv());
|
||||
LogSystemRegister(NZCV);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -3027,8 +3191,14 @@ void Simulator::VisitSystem(Instruction* instr) {
|
||||
}
|
||||
case MSR: {
|
||||
switch (instr->ImmSystemRegister()) {
|
||||
case NZCV: nzcv().SetRawValue(xreg(instr->Rt())); break;
|
||||
case FPCR: fpcr().SetRawValue(xreg(instr->Rt())); break;
|
||||
case NZCV:
|
||||
nzcv().SetRawValue(xreg(instr->Rt()));
|
||||
LogSystemRegister(NZCV);
|
||||
break;
|
||||
case FPCR:
|
||||
fpcr().SetRawValue(xreg(instr->Rt()));
|
||||
LogSystemRegister(FPCR);
|
||||
break;
|
||||
default: UNIMPLEMENTED();
|
||||
}
|
||||
break;
|
||||
@ -3239,8 +3409,8 @@ void Simulator::Debug() {
|
||||
} else if ((strcmp(cmd, "print") == 0) || (strcmp(cmd, "p") == 0)) {
|
||||
if (argc == 2) {
|
||||
if (strcmp(arg1, "all") == 0) {
|
||||
PrintRegisters(true);
|
||||
PrintFPRegisters(true);
|
||||
PrintRegisters();
|
||||
PrintFPRegisters();
|
||||
} else {
|
||||
if (!PrintValue(arg1)) {
|
||||
PrintF("%s unrecognized\n", arg1);
|
||||
@ -3444,7 +3614,7 @@ void Simulator::VisitException(Instruction* instr) {
|
||||
if (FLAG_trace_sim_messages || FLAG_trace_sim || (parameters & BREAK)) {
|
||||
if (message != NULL) {
|
||||
PrintF(stream_,
|
||||
"%sDebugger hit %d: %s%s%s\n",
|
||||
"# %sDebugger hit %d: %s%s%s\n",
|
||||
clr_debug_number,
|
||||
code,
|
||||
clr_debug_message,
|
||||
@ -3452,7 +3622,7 @@ void Simulator::VisitException(Instruction* instr) {
|
||||
clr_normal);
|
||||
} else {
|
||||
PrintF(stream_,
|
||||
"%sDebugger hit %d.%s\n",
|
||||
"# %sDebugger hit %d.%s\n",
|
||||
clr_debug_number,
|
||||
code,
|
||||
clr_normal);
|
||||
@ -3479,9 +3649,9 @@ void Simulator::VisitException(Instruction* instr) {
|
||||
// Don't print information that is already being traced.
|
||||
parameters &= ~log_parameters();
|
||||
// Print the requested information.
|
||||
if (parameters & LOG_SYS_REGS) PrintSystemRegisters(true);
|
||||
if (parameters & LOG_REGS) PrintRegisters(true);
|
||||
if (parameters & LOG_FP_REGS) PrintFPRegisters(true);
|
||||
if (parameters & LOG_SYS_REGS) PrintSystemRegisters();
|
||||
if (parameters & LOG_REGS) PrintRegisters();
|
||||
if (parameters & LOG_FP_REGS) PrintFPRegisters();
|
||||
}
|
||||
|
||||
// The stop parameters are inlined in the code. Skip them:
|
||||
|
||||
@ -312,7 +312,6 @@ class Simulator : public DecoderVisitor {
|
||||
DCHECK(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
|
||||
CheckBreakNext();
|
||||
Decode(pc_);
|
||||
LogProcessorState();
|
||||
increment_pc();
|
||||
CheckBreakpoints();
|
||||
}
|
||||
@ -348,16 +347,13 @@ class Simulator : public DecoderVisitor {
|
||||
return reg<int64_t>(code, r31mode);
|
||||
}
|
||||
|
||||
// Write 'size' bits of 'value' into an integer register. The value is
|
||||
// zero-extended. This behaviour matches AArch64 register writes.
|
||||
|
||||
// Like set_reg(), but infer the access size from the template type.
|
||||
// Write 'value' into an integer register. The value is zero-extended. This
|
||||
// behaviour matches AArch64 register writes.
|
||||
template<typename T>
|
||||
void set_reg(unsigned code, T value,
|
||||
Reg31Mode r31mode = Reg31IsZeroRegister) {
|
||||
DCHECK(code < kNumberOfRegisters);
|
||||
if (!IsZeroRegister(code, r31mode))
|
||||
registers_[code].Set(value);
|
||||
set_reg_no_log(code, value, r31mode);
|
||||
LogRegister(code, r31mode);
|
||||
}
|
||||
|
||||
// Common specialized accessors for the set_reg() template.
|
||||
@ -371,6 +367,26 @@ class Simulator : public DecoderVisitor {
|
||||
set_reg(code, value, r31mode);
|
||||
}
|
||||
|
||||
// As above, but don't automatically log the register update.
|
||||
template <typename T>
|
||||
void set_reg_no_log(unsigned code, T value,
|
||||
Reg31Mode r31mode = Reg31IsZeroRegister) {
|
||||
DCHECK(code < kNumberOfRegisters);
|
||||
if (!IsZeroRegister(code, r31mode)) {
|
||||
registers_[code].Set(value);
|
||||
}
|
||||
}
|
||||
|
||||
void set_wreg_no_log(unsigned code, int32_t value,
|
||||
Reg31Mode r31mode = Reg31IsZeroRegister) {
|
||||
set_reg_no_log(code, value, r31mode);
|
||||
}
|
||||
|
||||
void set_xreg_no_log(unsigned code, int64_t value,
|
||||
Reg31Mode r31mode = Reg31IsZeroRegister) {
|
||||
set_reg_no_log(code, value, r31mode);
|
||||
}
|
||||
|
||||
// Commonly-used special cases.
|
||||
template<typename T>
|
||||
void set_lr(T value) {
|
||||
@ -430,9 +446,13 @@ class Simulator : public DecoderVisitor {
|
||||
// This behaviour matches AArch64 register writes.
|
||||
template<typename T>
|
||||
void set_fpreg(unsigned code, T value) {
|
||||
DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
|
||||
DCHECK(code < kNumberOfFPRegisters);
|
||||
fpregisters_[code].Set(value);
|
||||
set_fpreg_no_log(code, value);
|
||||
|
||||
if (sizeof(value) <= kSRegSize) {
|
||||
LogFPRegister(code, kPrintSRegValue);
|
||||
} else {
|
||||
LogFPRegister(code, kPrintDRegValue);
|
||||
}
|
||||
}
|
||||
|
||||
// Common specialized accessors for the set_fpreg() template.
|
||||
@ -452,6 +472,22 @@ class Simulator : public DecoderVisitor {
|
||||
set_fpreg(code, value);
|
||||
}
|
||||
|
||||
// As above, but don't automatically log the register update.
|
||||
template <typename T>
|
||||
void set_fpreg_no_log(unsigned code, T value) {
|
||||
DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
|
||||
DCHECK(code < kNumberOfFPRegisters);
|
||||
fpregisters_[code].Set(value);
|
||||
}
|
||||
|
||||
void set_sreg_no_log(unsigned code, float value) {
|
||||
set_fpreg_no_log(code, value);
|
||||
}
|
||||
|
||||
void set_dreg_no_log(unsigned code, double value) {
|
||||
set_fpreg_no_log(code, value);
|
||||
}
|
||||
|
||||
SimSystemRegister& nzcv() { return nzcv_; }
|
||||
SimSystemRegister& fpcr() { return fpcr_; }
|
||||
|
||||
@ -478,33 +514,68 @@ class Simulator : public DecoderVisitor {
|
||||
// Disassemble instruction at the given address.
|
||||
void PrintInstructionsAt(Instruction* pc, uint64_t count);
|
||||
|
||||
void PrintSystemRegisters(bool print_all = false);
|
||||
void PrintRegisters(bool print_all_regs = false);
|
||||
void PrintFPRegisters(bool print_all_regs = false);
|
||||
void PrintProcessorState();
|
||||
void PrintWrite(uintptr_t address, uint64_t value, unsigned num_bytes);
|
||||
// Print all registers of the specified types.
|
||||
void PrintRegisters();
|
||||
void PrintFPRegisters();
|
||||
void PrintSystemRegisters();
|
||||
|
||||
// Like Print* (above), but respect log_parameters().
|
||||
void LogSystemRegisters() {
|
||||
if (log_parameters_ & LOG_SYS_REGS) PrintSystemRegisters();
|
||||
if (log_parameters() & LOG_SYS_REGS) PrintSystemRegisters();
|
||||
}
|
||||
void LogRegisters() {
|
||||
if (log_parameters_ & LOG_REGS) PrintRegisters();
|
||||
if (log_parameters() & LOG_REGS) PrintRegisters();
|
||||
}
|
||||
void LogFPRegisters() {
|
||||
if (log_parameters_ & LOG_FP_REGS) PrintFPRegisters();
|
||||
if (log_parameters() & LOG_FP_REGS) PrintFPRegisters();
|
||||
}
|
||||
void LogProcessorState() {
|
||||
LogSystemRegisters();
|
||||
LogRegisters();
|
||||
LogFPRegisters();
|
||||
|
||||
// Specify relevant register sizes, for PrintFPRegister.
|
||||
//
|
||||
// These values are bit masks; they can be combined in case multiple views of
|
||||
// a machine register are interesting.
|
||||
enum PrintFPRegisterSizes {
|
||||
kPrintDRegValue = 1 << kDRegSize,
|
||||
kPrintSRegValue = 1 << kSRegSize,
|
||||
kPrintAllFPRegValues = kPrintDRegValue | kPrintSRegValue,
|
||||
};
|
||||
|
||||
// Print individual register values (after update).
|
||||
void PrintRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer);
|
||||
void PrintFPRegister(unsigned code,
|
||||
PrintFPRegisterSizes sizes = kPrintAllFPRegValues);
|
||||
void PrintSystemRegister(SystemRegister id);
|
||||
|
||||
// Like Print* (above), but respect log_parameters().
|
||||
void LogRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer) {
|
||||
if (log_parameters() & LOG_REGS) PrintRegister(code, r31mode);
|
||||
}
|
||||
template <typename T>
|
||||
void LogWrite(uintptr_t address, T value) {
|
||||
uint64_t raw_value = 0;
|
||||
DCHECK(sizeof(value) <= sizeof(raw_value));
|
||||
if (log_parameters_ & LOG_WRITE) {
|
||||
memcpy(&raw_value, &value, sizeof(value));
|
||||
PrintWrite(address, raw_value, sizeof(value));
|
||||
}
|
||||
void LogFPRegister(unsigned code,
|
||||
PrintFPRegisterSizes sizes = kPrintAllFPRegValues) {
|
||||
if (log_parameters() & LOG_FP_REGS) PrintFPRegister(code, sizes);
|
||||
}
|
||||
void LogSystemRegister(SystemRegister id) {
|
||||
if (log_parameters() & LOG_SYS_REGS) PrintSystemRegister(id);
|
||||
}
|
||||
|
||||
// Print memory accesses.
|
||||
void PrintRead(uintptr_t address, size_t size, unsigned reg_code);
|
||||
void PrintReadFP(uintptr_t address, size_t size, unsigned reg_code);
|
||||
void PrintWrite(uintptr_t address, size_t size, unsigned reg_code);
|
||||
void PrintWriteFP(uintptr_t address, size_t size, unsigned reg_code);
|
||||
|
||||
// Like Print* (above), but respect log_parameters().
|
||||
void LogRead(uintptr_t address, size_t size, unsigned reg_code) {
|
||||
if (log_parameters() & LOG_REGS) PrintRead(address, size, reg_code);
|
||||
}
|
||||
void LogReadFP(uintptr_t address, size_t size, unsigned reg_code) {
|
||||
if (log_parameters() & LOG_FP_REGS) PrintReadFP(address, size, reg_code);
|
||||
}
|
||||
void LogWrite(uintptr_t address, size_t size, unsigned reg_code) {
|
||||
if (log_parameters() & LOG_WRITE) PrintWrite(address, size, reg_code);
|
||||
}
|
||||
void LogWriteFP(uintptr_t address, size_t size, unsigned reg_code) {
|
||||
if (log_parameters() & LOG_WRITE) PrintWriteFP(address, size, reg_code);
|
||||
}
|
||||
|
||||
int log_parameters() { return log_parameters_; }
|
||||
@ -595,14 +666,14 @@ class Simulator : public DecoderVisitor {
|
||||
int64_t offset,
|
||||
AddrMode addrmode);
|
||||
void LoadStorePairHelper(Instruction* instr, AddrMode addrmode);
|
||||
uint8_t* LoadStoreAddress(unsigned addr_reg,
|
||||
int64_t offset,
|
||||
AddrMode addrmode);
|
||||
uintptr_t LoadStoreAddress(unsigned addr_reg, int64_t offset,
|
||||
AddrMode addrmode);
|
||||
void LoadStoreWriteBack(unsigned addr_reg,
|
||||
int64_t offset,
|
||||
AddrMode addrmode);
|
||||
void CheckMemoryAccess(uint8_t* address, uint8_t* stack);
|
||||
void CheckMemoryAccess(uintptr_t address, uintptr_t stack);
|
||||
|
||||
// Memory read helpers.
|
||||
template <typename T, typename A>
|
||||
T MemoryRead(A address) {
|
||||
T value;
|
||||
@ -612,11 +683,11 @@ class Simulator : public DecoderVisitor {
|
||||
return value;
|
||||
}
|
||||
|
||||
// Memory write helpers.
|
||||
template <typename T, typename A>
|
||||
void MemoryWrite(A address, T value) {
|
||||
STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
|
||||
(sizeof(value) == 4) || (sizeof(value) == 8));
|
||||
LogWrite(reinterpret_cast<uintptr_t>(address), value);
|
||||
memcpy(reinterpret_cast<void*>(address), &value, sizeof(value));
|
||||
}
|
||||
|
||||
@ -771,10 +842,10 @@ class Simulator : public DecoderVisitor {
|
||||
static const uint32_t kConditionFlagsMask = 0xf0000000;
|
||||
|
||||
// Stack
|
||||
byte* stack_;
|
||||
static const intptr_t stack_protection_size_ = KB;
|
||||
intptr_t stack_size_;
|
||||
byte* stack_limit_;
|
||||
uintptr_t stack_;
|
||||
static const size_t stack_protection_size_ = KB;
|
||||
size_t stack_size_;
|
||||
uintptr_t stack_limit_;
|
||||
|
||||
Decoder<DispatchingDecoderVisitor>* decoder_;
|
||||
Decoder<DispatchingDecoderVisitor>* disassembler_decoder_;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user