MIPS: updated atomic operations.
Specifically: -fixed a bug in CompareAndSwap that caused randomly occuring timeouts on MIPS boards. -added gcc inline asm control push/pop instructions to correctly save/restore the reorder setting instead of simply assuming it should be enabled. -reordered/optimized some instructions to utilize MIPS-specific pipelining features (branch delay slot). -fixed improper usage of write barriers BUG= TEST= Review URL: http://codereview.chromium.org/8413073 Patch from Gergely Kis <gergely@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@9845 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -30,7 +30,7 @@
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#ifndef V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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#ifndef V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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#define V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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#define V8_ATOMICOPS_INTERNALS_MIPS_GCC_H_
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("sync" : : : "memory")
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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namespace v8 {
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namespace v8 {
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namespace internal {
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namespace internal {
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@ -48,16 +48,19 @@ namespace internal {
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 new_value) {
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Atomic32 prev;
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Atomic32 prev, tmp;
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__asm__ __volatile__("1:\n"
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__asm__ __volatile__(".set push\n"
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"ll %0, %1\n" // prev = *ptr
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".set noreorder\n"
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"1:\n"
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"ll %0, %5\n" // prev = *ptr
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"bne %0, %3, 2f\n" // if (prev != old_value) goto 2
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"bne %0, %3, 2f\n" // if (prev != old_value) goto 2
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"nop\n" // delay slot nop
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"move %2, %4\n" // tmp = new_value
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"sc %2, %1\n" // *ptr = new_value (with atomic check)
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"sc %2, %1\n" // *ptr = tmp (with atomic check)
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"beqz %2, 1b\n" // start again on atomic error
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"beqz %2, 1b\n" // start again on atomic error
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"nop\n" // delay slot nop
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"nop\n" // delay slot nop
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"2:\n"
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"2:\n"
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: "=&r" (prev), "=m" (*ptr), "+&r" (new_value)
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".set pop\n"
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: "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
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: "Ir" (old_value), "r" (new_value), "m" (*ptr)
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: "Ir" (old_value), "r" (new_value), "m" (*ptr)
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: "memory");
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: "memory");
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return prev;
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return prev;
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@ -68,12 +71,15 @@ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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Atomic32 new_value) {
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Atomic32 temp, old;
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Atomic32 temp, old;
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__asm__ __volatile__("1:\n"
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__asm__ __volatile__(".set push\n"
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".set noreorder\n"
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"1:\n"
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"ll %1, %2\n" // old = *ptr
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"ll %1, %2\n" // old = *ptr
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"move %0, %3\n" // temp = new_value
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"move %0, %3\n" // temp = new_value
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"sc %0, %2\n" // *ptr = temp (with atomic check)
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"sc %0, %2\n" // *ptr = temp (with atomic check)
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"beqz %0, 1b\n" // start again on atomic error
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"beqz %0, 1b\n" // start again on atomic error
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"nop\n" // delay slot nop
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"nop\n" // delay slot nop
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".set pop\n"
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: "=&r" (temp), "=&r" (old), "=m" (*ptr)
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: "=&r" (temp), "=&r" (old), "=m" (*ptr)
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: "r" (new_value), "m" (*ptr)
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: "r" (new_value), "m" (*ptr)
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: "memory");
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: "memory");
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@ -87,13 +93,15 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 increment) {
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Atomic32 temp, temp2;
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Atomic32 temp, temp2;
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__asm__ __volatile__("1:\n"
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__asm__ __volatile__(".set push\n"
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".set noreorder\n"
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"1:\n"
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"ll %0, %2\n" // temp = *ptr
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"ll %0, %2\n" // temp = *ptr
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"addu %0, %3\n" // temp = temp + increment
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"addu %1, %0, %3\n" // temp2 = temp + increment
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"move %1, %0\n" // temp2 = temp
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"sc %1, %2\n" // *ptr = temp2 (with atomic check)
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"sc %0, %2\n" // *ptr = temp (with atomic check)
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"beqz %1, 1b\n" // start again on atomic error
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"beqz %0, 1b\n" // start again on atomic error
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"addu %1, %0, %3\n" // temp2 = temp + increment
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"nop\n" // delay slot nop
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".set pop\n"
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: "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
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: "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
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: "Ir" (increment), "m" (*ptr)
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: "Ir" (increment), "m" (*ptr)
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: "memory");
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: "memory");
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@ -103,6 +111,7 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 increment) {
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ATOMICOPS_COMPILER_BARRIER();
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Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
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Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
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ATOMICOPS_COMPILER_BARRIER();
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ATOMICOPS_COMPILER_BARRIER();
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return res;
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return res;
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@ -117,16 +126,19 @@ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 new_value) {
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Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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ATOMICOPS_COMPILER_BARRIER();
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ATOMICOPS_COMPILER_BARRIER();
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return x;
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Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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ATOMICOPS_COMPILER_BARRIER();
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return res;
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}
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 new_value) {
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ATOMICOPS_COMPILER_BARRIER();
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ATOMICOPS_COMPILER_BARRIER();
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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ATOMICOPS_COMPILER_BARRIER();
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return res;
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}
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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@ -134,7 +146,7 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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}
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}
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inline void MemoryBarrier() {
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inline void MemoryBarrier() {
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ATOMICOPS_COMPILER_BARRIER();
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__asm__ __volatile__("sync" : : : "memory");
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}
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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