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PPC [wasm-simd]: prototype i64x2 widen i32x4

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Bug: v8:10972
Change-Id: I76d795c1f4cf0fc39ca4b4f4ea72c8e817c17da5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2632699
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72152}
This commit is contained in:
Milad Fa 2021-01-18 12:11:31 -05:00 committed by Commit Bot
parent 7819b1b579
commit d044486855
4 changed files with 44 additions and 2 deletions
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4
src/codegen/ppc/constants-ppc.h
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@ -2393,6 +2393,8 @@ using Instr = uint32_t;
V(vbpermq, VBPERMQ, 0x1000054C)
#define PPC_VX_OPCODE_C_FORM_LIST(V) \
/* Vector Unpack Low Signed Word */ \
V(vupklsw, VUPKLSW, 0x100006CE) \
/* Vector Unpack High Signed Word */ \
V(vupkhsw, VUPKHSW, 0x1000064E) \
/* Vector Unpack Low Signed Halfword */ \
@ -2559,8 +2561,6 @@ using Instr = uint32_t;
V(vupkhpx, VUPKHPX, 0x1000034E) \
/* Vector Unpack Low Pixel */ \
V(vupklpx, VUPKLPX, 0x100003CE) \
/* Vector Unpack Low Signed Word */ \
V(vupklsw, VUPKLSW, 0x100006CE) \
/* Vector AES Cipher */ \
V(vcipher, VCIPHER, 0x10000508) \
/* Vector AES Cipher Last */ \

34
src/compiler/backend/ppc/code-generator-ppc.cc
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@ -3100,6 +3100,40 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ xvcvuxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2SConvertI32x4Low: {
__ vupklsw(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2SConvertI32x4High: {
__ vupkhsw(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2UConvertI32x4Low: {
constexpr int lane_width_in_bytes = 8;
__ vupklsw(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ mov(ip, Operand(0xFFFFFFFF));
__ mtvsrd(kScratchSimd128Reg, ip);
__ vinsertd(kScratchSimd128Reg, kScratchSimd128Reg,
Operand(1 * lane_width_in_bytes));
__ vand(i.OutputSimd128Register(), kScratchSimd128Reg,
i.OutputSimd128Register());
break;
}
case kPPC_I64x2UConvertI32x4High: {
constexpr int lane_width_in_bytes = 8;
__ vupkhsw(i.OutputSimd128Register(), i.InputSimd128Register(0));
// Zero extend.
__ mov(ip, Operand(0xFFFFFFFF));
__ mtvsrd(kScratchSimd128Reg, ip);
__ vinsertd(kScratchSimd128Reg, kScratchSimd128Reg,
Operand(1 * lane_width_in_bytes));
__ vand(i.OutputSimd128Register(), kScratchSimd128Reg,
i.OutputSimd128Register());
break;
}
case kPPC_I32x4SConvertI16x8Low: {
__ vupklsh(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;

4
src/compiler/backend/ppc/instruction-codes-ppc.h
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@ -264,6 +264,10 @@ namespace compiler {
V(PPC_I64x2ShrU) \
V(PPC_I64x2Neg) \
V(PPC_I64x2BitMask) \
V(PPC_I64x2SConvertI32x4Low) \
V(PPC_I64x2SConvertI32x4High) \
V(PPC_I64x2UConvertI32x4Low) \
V(PPC_I64x2UConvertI32x4High) \
V(PPC_I32x4Splat) \
V(PPC_I32x4ExtractLane) \
V(PPC_I32x4ReplaceLane) \

4
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
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@ -189,6 +189,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I64x2ShrU:
case kPPC_I64x2Neg:
case kPPC_I64x2BitMask:
case kPPC_I64x2SConvertI32x4Low:
case kPPC_I64x2SConvertI32x4High:
case kPPC_I64x2UConvertI32x4Low:
case kPPC_I64x2UConvertI32x4High:
case kPPC_I32x4Splat:
case kPPC_I32x4ExtractLane:
case kPPC_I32x4ReplaceLane: