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[riscv] Fix cctest/test-assembler-riscv64/RISCV_UTEST_swlwu.

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32-bit values are held in a sign-extended format in 64-bit registers. Which
the vaule 0x856AF894 becomes 0xFFFFFFFF856AF894 and failed equality comparison
with lwu's result 0x00000000856AF894. XOR the result with 0xFFFFFFFF00000000
before comparison.

R=yahan@iscas.ac.cn

Change-Id: I4d225ff653070022023ac7f10257ad0c30c24e5b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3881601
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#83109}
This commit is contained in:
Ting Chou 2022-09-08 16:06:37 +08:00 committed by V8 LUCI CQ
parent 53d24ef68b
commit d17bc74fc0
1 changed files with 9 additions and 4 deletions
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13
test/cctest/test-helper-riscv64.h
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@ -177,6 +177,10 @@ template <typename T>
void GenAndRunTestForLoadStore(T value, Func test_generator) {
DCHECK(sizeof(T) == 4 || sizeof(T) == 8);
using INT_T = typename std::conditional<
std::is_integral<T>::value, T,
typename std::conditional<sizeof(T) == 4, int32_t, int64_t>::type>::type;
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
@ -194,6 +198,11 @@ void GenAndRunTestForLoadStore(T value, Func test_generator) {
assm.fmv_x_w(a0, fa0);
} else if (std::is_same<double, T>::value) {
assm.fmv_x_d(a0, fa0);
} else if (std::is_same<uint32_t, T>::value) {
if (base::bit_cast<INT_T>(value) & 0x80000000) {
assm.RV_li(t5, 0xffffffff00000000);
assm.xor_(a0, a0, t5);
}
}
assm.jr(ra);
@ -202,10 +211,6 @@ void GenAndRunTestForLoadStore(T value, Func test_generator) {
Handle<Code> code =
Factory::CodeBuilder(isolate, desc, CodeKind::FOR_TESTING).Build();
using INT_T = typename std::conditional<
std::is_integral<T>::value, T,
typename std::conditional<sizeof(T) == 4, int32_t, int64_t>::type>::type;
auto f = GeneratedCode<INT_T(void* base, INT_T val)>::FromCode(*code);
int64_t tmp = 0;