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[cctest] Skip test-run-wasm-simd if SIMD is not supported

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For mips, if 'mips_arch_variant=="r6"' and if 'mips_use_msa' flag is set
to 'true', then test-run-wasm-simd tests won't be skipped for mips. It
will also force 'MIPS_SIMD' bit in CpuFeatures to be set.
ARM processors are assumed to support SIMD.

Change-Id: Iea668b97ef995ca4949ddbf2ffc734aad89d3aa3
Reviewed-on: https://chromium-review.googlesource.com/868430
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#50981}
This commit is contained in:
Predrag Rudic 2018-01-29 11:24:31 +01:00 committed by Commit Bot
parent 8e7737cb58
commit d2ad89d846
10 changed files with 138 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
BUILD.gn
View File

@ -387,6 +387,9 @@ config("toolchain") {
"_MIPS_ARCH_MIPS32R6",
"FPU_MODE_FP64",
]
if (mips_use_msa) {
defines += [ "_MIPS_MSA" ]
}
} else if (mips_arch_variant == "r2") {
defines += [ "_MIPS_ARCH_MIPS32R2" ]
if (mips_fpu_mode == "fp64") {
@ -424,6 +427,9 @@ config("toolchain") {
}
if (mips_arch_variant == "r6") {
defines += [ "_MIPS_ARCH_MIPS64R6" ]
if (mips_use_msa) {
defines += [ "_MIPS_MSA" ]
}
} else if (mips_arch_variant == "r2") {
defines += [ "_MIPS_ARCH_MIPS64R2" ]
}
@ -883,6 +889,14 @@ action("v8_dump_build_config") {
"v8_target_cpu=\"$v8_target_cpu\"",
"v8_use_snapshot=$v8_use_snapshot",
]
if (v8_current_cpu == "mips" || v8_current_cpu == "mipsel" ||
v8_current_cpu == "mips64" || v8_current_cpu == "mips64el") {
args += [
"mips_arch_variant=\"$mips_arch_variant\"",
"mips_use_msa=$mips_use_msa",
]
}
}
###############################################################################

30
gypfiles/toolchain.gypi
View File

@ -58,6 +58,9 @@
# Similar to the ARM hard float ABI but on MIPS.
'v8_use_mips_abi_hardfloat%': 'true',
# MIPS MSA support
'mips_use_msa%': 0,
# Print to stdout on Android.
'v8_android_log_stdout%': 0,
@ -439,6 +442,9 @@
'cflags': ['-mips32r6'],
'ldflags': ['-mips32r6'],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
[ 'mips_fpu_mode=="fp64"', {
@ -507,6 +513,9 @@
'FPU_MODE_FP64',
],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
[ 'mips_fpu_mode=="fp64"', {
@ -558,6 +567,9 @@
'FPU_MODE_FP64',
],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
['mips_fpu_mode=="fp64"', {
@ -640,6 +652,9 @@
'cflags': ['-mips32r6'],
'ldflags': ['-mips32r6'],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
[ 'mips_fpu_mode=="fp64"', {
@ -721,6 +736,9 @@
'FPU_MODE_FP64',
],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
[ 'mips_fpu_mode=="fp64"', {
@ -778,6 +796,9 @@
'FPU_MODE_FP64',
],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'conditions': [
['mips_fpu_mode=="fp64"', {
@ -877,6 +898,9 @@
'cflags': ['-mips64r6', '-mabi=64'],
'ldflags': ['-mips64r6', '-mabi=64'],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'defines': ['_MIPS_ARCH_MIPS64R2',],
'conditions': [
@ -895,6 +919,9 @@
['mips_arch_variant=="r6"', {
'defines': ['_MIPS_ARCH_MIPS64R6',],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'defines': ['_MIPS_ARCH_MIPS64R2',],
}],
@ -907,6 +934,9 @@
['mips_arch_variant=="r6"', {
'defines': ['_MIPS_ARCH_MIPS64R6',],
}],
['mips_arch_variant=="r6" and mips_use_msa==1', {
'defines': [ '_MIPS_MSA' ],
}],
['mips_arch_variant=="r2"', {
'defines': ['_MIPS_ARCH_MIPS64R2',],
}],

9
gypfiles/v8.gyp
View File

@ -2555,6 +2555,15 @@
'v8_target_cpu=<(v8_target_arch)',
'v8_use_snapshot=<(v8_use_snapshot)',
],
'conditions': [
['v8_target_arch=="mips" or v8_target_arch=="mipsel" \
or v8_target_arch=="mips64" or v8_target_arch=="mips64el"', {
'action':[
'mips_arch_variant=<(mips_arch_variant)',
'mips_use_msa=<(mips_use_msa)',
],
}],
],
},
],
},

3
src/base/cpu.cc
View File

@ -335,7 +335,8 @@ CPU::CPU()
has_vfp3_(false),
has_vfp3_d32_(false),
is_fp64_mode_(false),
has_non_stop_time_stamp_counter_(false) {
has_non_stop_time_stamp_counter_(false),
has_msa_(false) {
memcpy(vendor_, "Unknown", 8);
#if V8_HOST_ARCH_IA32 || V8_HOST_ARCH_X64
int cpu_info[4];

9
src/mips/assembler-mips.cc
View File

@ -79,6 +79,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
#if defined(_MIPS_ARCH_MIPS32R6)
// FP64 mode is implied on r6.
supported_ |= 1u << FP64FPU;
#if defined(_MIPS_MSA)
supported_ |= 1u << MIPS_SIMD;
#endif
#endif
#if defined(FPU_MODE_FP64)
supported_ |= 1u << FP64FPU;
@ -91,8 +94,14 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (cpu.is_fp64_mode()) supported_ |= 1u << FP64FPU;
#elif defined(FPU_MODE_FP64)
supported_ |= 1u << FP64FPU;
#if defined(_MIPS_ARCH_MIPS32R6)
#if defined(_MIPS_MSA)
supported_ |= 1u << MIPS_SIMD;
#else
if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD;
#endif
#endif
#endif
#if defined(_MIPS_ARCH_MIPS32RX)
if (cpu.architecture() == 6) {
supported_ |= 1u << MIPSr6;

9
src/mips64/assembler-mips64.cc
View File

@ -76,12 +76,21 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
#ifndef __mips__
// For the simulator build, use FPU.
supported_ |= 1u << FPU;
#if defined(_MIPS_ARCH_MIPS64R6) && defined(_MIPS_MSA)
supported_ |= 1u << MIPS_SIMD;
#endif
#else
// Probe for additional features at runtime.
base::CPU cpu;
if (cpu.has_fpu()) supported_ |= 1u << FPU;
#if defined(_MIPS_ARCH_MIPS64R6)
#if defined(_MIPS_MSA)
supported_ |= 1u << MIPS_SIMD;
#else
if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD;
#endif
#endif
#endif
}

59
test/cctest/cctest.status
View File

@ -318,12 +318,59 @@
}], # 'arch == mips64el or arch == mips64'
##############################################################################
['arch == mips or arch == mipsel or arch == mips64 or arch == mips64el', {
# For now skip wasm SIMD tests that fail when MSA instr. extension is not
# available (currently simd-scalar-lowering mechanism doesn't work properly
# for all SIMD operations)
'test-run-wasm-simd/*': [SKIP],
}], # 'arch == mips or arch == mipsel or arch == mips64 or arch == mips64el'
['(arch == mipsel or arch == mips64el or arch == mips or arch == mips64) and not simd_mips', {
# Skip tests that fail on MIPS architectures which don't support SIMD,
# because lowering mechanism doesn't work properly
'test-run-wasm-simd/RunWasm_F32x4RecipApprox_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_F32x4RecipSqrtApprox_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I32x4ConvertI16x8_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I16x8ConvertI8x16_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I16x8ConvertI32x4_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I8x16ConvertI16x8_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4Select_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8Select_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16Select_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4NonCanonicalSelect_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8NonCanonicalSelect_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16NonCanonicalSelect_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I32x4AddHoriz_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_I16x8AddHoriz_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_F32x4AddHoriz_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4Dup_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4ZipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4ZipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4UnzipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4UnzipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4TransposeLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4TransposeRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x2Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S32x4Irregular_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8Dup_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8ZipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8ZipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8UnzipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8UnzipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8TransposeLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8TransposeRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x4Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x2Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S16x8Irregular_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16Dup_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16ZipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16ZipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16UnzipLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16UnzipRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16TransposeLeft_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16TransposeRight_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x8Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x4Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x2Reverse_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16Irregular_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_S8x16Concat_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_ReductionTest4_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_ReductionTest8_compiled': [SKIP],
'test-run-wasm-simd/RunWasm_ReductionTest16_compiled': [SKIP],
}], # '(arch == mipsel or arch == mips64el or arch == mips or arch == mips64) and not simd_mips'
##############################################################################
['arch == android_arm or arch == android_ia32', {

4
tools/testrunner/base_runner.py
View File

@ -163,6 +163,10 @@ class BuildConfig(object):
self.predictable = build_config['v8_enable_verify_predictable']
self.tsan = build_config['is_tsan']
self.ubsan_vptr = build_config['is_ubsan_vptr']
# Export only for MIPS target
if self.arch in ['mips', 'mipsel', 'mips64', 'mips64el']:
self.mips_arch_variant = build_config['mips_arch_variant']
self.mips_use_msa = build_config['mips_use_msa']
def __str__(self):
detected_options = []

1
tools/testrunner/num_fuzzer.py
View File

@ -270,6 +270,7 @@ class NumFuzzer(base_runner.BaseTestRunner):
"no_snap": self.build_config.no_snap,
"novfp3": False,
"predictable": self.build_config.predictable,
"simd_mips": True,
"simulator": utils.UseSimulator(self.build_config.arch),
"simulator_run": False,
"system": utils.GuessOS(),

7
tools/testrunner/standard_runner.py
View File

@ -389,6 +389,12 @@ class StandardTestRunner(base_runner.BaseTestRunner):
use_perf_data=not options.swarming,
sancov_dir=self.sancov_dir)
# simd_mips is true if SIMD is fully supported on MIPS
simd_mips = (
self.build_config.arch in [ 'mipsel', 'mips', 'mips64', 'mips64el'] and
self.build_config.mips_arch_variant == "r6" and
self.build_config.mips_use_msa)
# TODO(all): Combine "simulator" and "simulator_run".
# TODO(machenbach): In GN we can derive simulator run from
# target_arch != v8_target_arch in the dumped build config.
@ -419,6 +425,7 @@ class StandardTestRunner(base_runner.BaseTestRunner):
"predictable": self.build_config.predictable,
"simulator": utils.UseSimulator(self.build_config.arch),
"simulator_run": simulator_run,
"simd_mips": simd_mips,
"system": utils.GuessOS(),
"tsan": self.build_config.tsan,
"ubsan_vptr": self.build_config.ubsan_vptr,