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PPC: clear upper bits of some inputs before emitting

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Most register and immediate inputs are 5 bits long and 0x1f is used
as mask. Some immediates are byte sized in which case 0xff had to
be used.

Change-Id: Id7568732db9141743c839a2d1d21a27983547aba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3009811
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75644}
This commit is contained in:
Milad Fa 2021-07-07 14:01:27 -04:00 committed by V8 LUCI CQ
parent afec75548e
commit d31f77a0bc
2 changed files with 12 additions and 9 deletions
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3
src/codegen/ppc/assembler-ppc.cc
View File

@ -1912,7 +1912,8 @@ void Assembler::stxvx(const Simd128Register rt, const MemOperand& dst) {
void Assembler::xxspltib(const Simd128Register rt, const Operand& imm) {
int TX = 1;
CHECK(is_uint8(imm.immediate()));
emit(XXSPLTIB | rt.code() * B21 | imm.immediate() * B11 | TX);
emit(XXSPLTIB | (rt.code() & 0x1F) * B21 | (imm.immediate() & 0xFF) * B11 |
TX);
}
// Pseudo instructions.

18
src/codegen/ppc/assembler-ppc.h
View File

@ -495,17 +495,19 @@ class Assembler : public AssemblerBase {
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb,
const Operand& imm) {
emit(instr | rt.code() * B21 | imm.immediate() * B16 | rb.code() * B11);
emit(instr | (rt.code() & 0x1F) * B21 | (imm.immediate() & 0x1F) * B16 |
(rb.code() & 0x1F) * B11);
}
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11);
emit(instr | (rt.code() & 0x1F) * B21 | ra.code() * B16 |
(rb.code() & 0x1F) * B11);
}
inline void vx_form(Instr instr, Simd128Register rt, Simd128Register rb) {
emit(instr | rt.code() * B21 | rb.code() * B11);
emit(instr | (rt.code() & 0x1F) * B21 | (rb.code() & 0x1F) * B11);
}
inline void vx_form(Instr instr, Simd128Register rt, const Operand& imm) {
emit(instr | rt.code() * B21 | (imm.immediate() & 0x1F) * B16);
emit(instr | (rt.code() & 0x1F) * B21 | (imm.immediate() & 0x1F) * B16);
}
PPC_VX_OPCODE_A_FORM_LIST(DECLARE_PPC_VX_INSTRUCTIONS_A_FORM)
@ -528,8 +530,8 @@ class Assembler : public AssemblerBase {
inline void va_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb, Simd128Register rc) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc.code() * B6);
emit(instr | (rt.code() & 0x1F) * B21 | (ra.code() & 0x1F) * B16 |
(rb.code() & 0x1F) * B11 | (rc.code() & 0x1F) * B6);
}
PPC_VA_OPCODE_A_FORM_LIST(DECLARE_PPC_VA_INSTRUCTIONS_A_FORM)
@ -543,8 +545,8 @@ class Assembler : public AssemblerBase {
inline void vc_form(Instr instr, Simd128Register rt, Simd128Register ra,
Simd128Register rb, int rc) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
rc * B10);
emit(instr | (rt.code() & 0x1F) * B21 | (ra.code() & 0x1F) * B16 |
(rb.code() & 0x1F) * B11 | rc * B10);
}
PPC_VC_OPCODE_LIST(DECLARE_PPC_VC_INSTRUCTIONS)