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PPC: [wasm-simd] Remove some I64x2 instructions not in proposal

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This is a partial port of :
2c38a47752

Some of the opcodes were added back in later CLs.

Change-Id: Iba33b0930f5b7ec95cdbe6febaa38766a9a6344f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2826238
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73964}
This commit is contained in:
Milad Fa 2021-04-14 14:58:28 -04:00 committed by Commit Bot
parent cb491810aa
commit d338a86b67
3 changed files with 0 additions and 47 deletions
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35
src/compiler/backend/ppc/code-generator-ppc.cc
View File

@ -2479,21 +2479,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MinS: {
__ vminsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MinS: {
__ vminsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MinU: {
__ vminud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MinU: {
__ vminuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
@ -2519,21 +2509,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MaxS: {
__ vmaxsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MaxS: {
__ vmaxsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2MaxU: {
__ vmaxud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4MaxU: {
__ vmaxuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
@ -2679,27 +2659,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kScratchSimd128Reg);
break;
}
case kPPC_I64x2GtU: {
__ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I32x4GtU: {
__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kPPC_I64x2GeU: {
__ vcmpequd(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchSimd128Reg);
break;
}
case kPPC_I32x4GeU: {
__ vcmpequw(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));

6
src/compiler/backend/ppc/instruction-codes-ppc.h
View File

@ -255,15 +255,9 @@ namespace compiler {
V(PPC_I64x2Add) \
V(PPC_I64x2Sub) \
V(PPC_I64x2Mul) \
V(PPC_I64x2MinS) \
V(PPC_I64x2MinU) \
V(PPC_I64x2MaxS) \
V(PPC_I64x2MaxU) \
V(PPC_I64x2Eq) \
V(PPC_I64x2Ne) \
V(PPC_I64x2GtS) \
V(PPC_I64x2GtU) \
V(PPC_I64x2GeU) \
V(PPC_I64x2GeS) \
V(PPC_I64x2Shl) \
V(PPC_I64x2ShrS) \

6
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View File

@ -177,15 +177,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I64x2Add:
case kPPC_I64x2Sub:
case kPPC_I64x2Mul:
case kPPC_I64x2MinS:
case kPPC_I64x2MinU:
case kPPC_I64x2MaxS:
case kPPC_I64x2MaxU:
case kPPC_I64x2Eq:
case kPPC_I64x2Ne:
case kPPC_I64x2GtS:
case kPPC_I64x2GtU:
case kPPC_I64x2GeU:
case kPPC_I64x2GeS:
case kPPC_I64x2Shl:
case kPPC_I64x2ShrS: