[turbofan] add new x64 addressing modes
R=bmeurer@chromium.org, titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/605693002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
dcarney@chromium.org
parent
ad24cdae72
commit
d3a021bbe0
@ -107,10 +107,10 @@ typedef int32_t InstructionCode;
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// continuation into a single InstructionCode which is stored as part of
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// the instruction.
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typedef BitField<ArchOpcode, 0, 7> ArchOpcodeField;
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typedef BitField<AddressingMode, 7, 4> AddressingModeField;
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typedef BitField<FlagsMode, 11, 2> FlagsModeField;
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typedef BitField<FlagsCondition, 13, 5> FlagsConditionField;
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typedef BitField<int, 13, 19> MiscField;
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typedef BitField<AddressingMode, 7, 5> AddressingModeField;
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typedef BitField<FlagsMode, 12, 2> FlagsModeField;
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typedef BitField<FlagsCondition, 14, 5> FlagsConditionField;
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typedef BitField<int, 14, 18> MiscField;
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} // namespace compiler
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} // namespace internal
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@ -145,22 +145,79 @@ class X64OperandConverter : public InstructionOperandConverter {
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return result;
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}
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Operand MemoryOperand(int* first_input) {
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const int offset = *first_input;
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switch (AddressingModeField::decode(instr_->opcode())) {
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case kMode_MR1I: {
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*first_input += 2;
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Register index = InputRegister(offset + 1);
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return Operand(InputRegister(offset + 0), index, times_1,
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0); // TODO(dcarney): K != 0
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static int NextOffset(int* offset) {
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int i = *offset;
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(*offset)++;
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return i;
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}
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static ScaleFactor ScaleFor(AddressingMode one, AddressingMode mode) {
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STATIC_ASSERT(0 == static_cast<int>(times_1));
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STATIC_ASSERT(1 == static_cast<int>(times_2));
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STATIC_ASSERT(2 == static_cast<int>(times_4));
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STATIC_ASSERT(3 == static_cast<int>(times_8));
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int scale = static_cast<int>(mode - one);
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DCHECK(scale >= 0 && scale < 4);
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return static_cast<ScaleFactor>(scale);
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}
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Operand MemoryOperand(int* offset) {
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AddressingMode mode = AddressingModeField::decode(instr_->opcode());
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switch (mode) {
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case kMode_MR: {
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Register base = InputRegister(NextOffset(offset));
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int32_t disp = 0;
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return Operand(base, disp);
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}
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case kMode_MRI:
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*first_input += 2;
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return Operand(InputRegister(offset + 0), InputInt32(offset + 1));
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default:
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case kMode_MRI: {
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Register base = InputRegister(NextOffset(offset));
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int32_t disp = InputInt32(NextOffset(offset));
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return Operand(base, disp);
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}
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case kMode_MR1:
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case kMode_MR2:
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case kMode_MR4:
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case kMode_MR8: {
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Register base = InputRegister(NextOffset(offset));
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Register index = InputRegister(NextOffset(offset));
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ScaleFactor scale = ScaleFor(kMode_MR1, mode);
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int32_t disp = 0;
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return Operand(base, index, scale, disp);
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}
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case kMode_MR1I:
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case kMode_MR2I:
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case kMode_MR4I:
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case kMode_MR8I: {
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Register base = InputRegister(NextOffset(offset));
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Register index = InputRegister(NextOffset(offset));
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ScaleFactor scale = ScaleFor(kMode_MR1I, mode);
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int32_t disp = InputInt32(NextOffset(offset));
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return Operand(base, index, scale, disp);
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}
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case kMode_M1:
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case kMode_M2:
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case kMode_M4:
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case kMode_M8: {
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Register index = InputRegister(NextOffset(offset));
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ScaleFactor scale = ScaleFor(kMode_M1, mode);
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int32_t disp = 0;
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return Operand(index, scale, disp);
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}
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case kMode_M1I:
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case kMode_M2I:
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case kMode_M4I:
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case kMode_M8I: {
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Register index = InputRegister(NextOffset(offset));
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ScaleFactor scale = ScaleFor(kMode_M1I, mode);
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int32_t disp = InputInt32(NextOffset(offset));
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return Operand(index, scale, disp);
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}
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case kMode_None:
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UNREACHABLE();
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return Operand(no_reg, 0);
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}
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UNREACHABLE();
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return Operand(no_reg, 0);
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}
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Operand MemoryOperand() {
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@ -79,22 +79,30 @@ namespace compiler {
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//
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// We use the following local notation for addressing modes:
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//
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// R = register
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// O = register or stack slot
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// D = double register
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// I = immediate (handle, external, int32)
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// MR = [register]
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// MI = [immediate]
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// MRN = [register + register * N in {1, 2, 4, 8}]
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// MRI = [register + immediate]
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// MRNI = [register + register * N in {1, 2, 4, 8} + immediate]
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// M = memory operand
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// R = base register
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// N = index register * N for N in {1, 2, 4, 8}
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// I = immediate displacement (int32_t)
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#define TARGET_ADDRESSING_MODE_LIST(V) \
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V(MR) /* [%r1] */ \
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V(MRI) /* [%r1 + K] */ \
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V(MR1I) /* [%r1 + %r2 + K] */ \
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V(MR) /* [%r1 ] */ \
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V(MRI) /* [%r1 + K] */ \
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V(MR1) /* [%r1 + %r2*1 ] */ \
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V(MR2) /* [%r1 + %r2*2 ] */ \
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V(MR4) /* [%r1 + %r2*4 ] */ \
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V(MR8) /* [%r1 + %r2*8 ] */ \
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V(MR1I) /* [%r1 + %r2*1 + K] */ \
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V(MR2I) /* [%r1 + %r2*2 + K] */ \
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V(MR4I) /* [%r1 + %r2*4 + K] */ \
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V(MR8I) /* [%r1 + %r2*8 + K] */
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V(MR4I) /* [%r1 + %r2*3 + K] */ \
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V(MR8I) /* [%r1 + %r2*4 + K] */ \
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V(M1) /* [ %r2*1 ] */ \
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V(M2) /* [ %r2*2 ] */ \
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V(M4) /* [ %r2*4 ] */ \
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V(M8) /* [ %r2*8 ] */ \
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V(M1I) /* [ %r2*1 + K] */ \
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V(M2I) /* [ %r2*2 + K] */ \
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V(M4I) /* [ %r2*4 + K] */ \
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V(M8I) /* [ %r2*8 + K] */
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} // namespace compiler
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} // namespace internal
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@ -161,6 +161,134 @@ INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorMemoryAccessTest,
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::testing::ValuesIn(kMemoryAccesses));
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// -----------------------------------------------------------------------------
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// AddressingMode for loads and stores.
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class AddressingModeUnitTest : public InstructionSelectorTest {
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public:
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AddressingModeUnitTest() : m(NULL) { Reset(); }
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~AddressingModeUnitTest() { delete m; }
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void Run(Node* base, Node* index, AddressingMode mode) {
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Node* load = m->Load(kMachInt32, base, index);
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m->Store(kMachInt32, base, index, load);
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m->Return(m->Int32Constant(0));
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Stream s = m->Build();
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ASSERT_EQ(2U, s.size());
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EXPECT_EQ(mode, s[0]->addressing_mode());
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EXPECT_EQ(mode, s[1]->addressing_mode());
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}
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Node* zero;
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Node* null_ptr;
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Node* non_zero;
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Node* base_reg; // opaque value to generate base as register
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Node* index_reg; // opaque value to generate index as register
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Node* scales[4];
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StreamBuilder* m;
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void Reset() {
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delete m;
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m = new StreamBuilder(this, kMachInt32, kMachInt32, kMachInt32);
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zero = m->Int32Constant(0);
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null_ptr = m->Int64Constant(0);
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non_zero = m->Int32Constant(127);
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base_reg = m->Parameter(0);
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index_reg = m->Parameter(0);
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scales[0] = m->Int32Constant(1);
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scales[1] = m->Int32Constant(2);
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scales[2] = m->Int32Constant(4);
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scales[3] = m->Int32Constant(8);
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}
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};
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TEST_F(AddressingModeUnitTest, AddressingMode_MR) {
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Node* base = base_reg;
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Node* index = zero;
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Run(base, index, kMode_MR);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MRI) {
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Node* base = base_reg;
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Node* index = non_zero;
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Run(base, index, kMode_MRI);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MR1) {
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Node* base = base_reg;
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Node* index = index_reg;
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Run(base, index, kMode_MR1);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MRN) {
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AddressingMode expected[] = {kMode_MR1, kMode_MR2, kMode_MR4, kMode_MR8};
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for (size_t i = 0; i < arraysize(scales); ++i) {
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Reset();
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Node* base = base_reg;
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Node* index = m->Int32Mul(index_reg, scales[i]);
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Run(base, index, expected[i]);
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}
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MR1I) {
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Node* base = base_reg;
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Node* index = m->Int32Add(index_reg, non_zero);
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Run(base, index, kMode_MR1I);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MRNI) {
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AddressingMode expected[] = {kMode_MR1I, kMode_MR2I, kMode_MR4I, kMode_MR8I};
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for (size_t i = 0; i < arraysize(scales); ++i) {
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Reset();
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Node* base = base_reg;
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Node* index = m->Int32Add(m->Int32Mul(index_reg, scales[i]), non_zero);
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Run(base, index, expected[i]);
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}
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_M1) {
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Node* base = null_ptr;
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Node* index = index_reg;
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Run(base, index, kMode_M1);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MN) {
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AddressingMode expected[] = {kMode_M1, kMode_M2, kMode_M4, kMode_M8};
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for (size_t i = 0; i < arraysize(scales); ++i) {
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Reset();
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Node* base = null_ptr;
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Node* index = m->Int32Mul(index_reg, scales[i]);
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Run(base, index, expected[i]);
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}
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_M1I) {
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Node* base = null_ptr;
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Node* index = m->Int32Add(index_reg, non_zero);
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Run(base, index, kMode_M1I);
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}
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TEST_F(AddressingModeUnitTest, AddressingMode_MNI) {
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AddressingMode expected[] = {kMode_M1I, kMode_M2I, kMode_M4I, kMode_M8I};
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for (size_t i = 0; i < arraysize(scales); ++i) {
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Reset();
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Node* base = null_ptr;
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Node* index = m->Int32Add(m->Int32Mul(index_reg, scales[i]), non_zero);
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Run(base, index, expected[i]);
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}
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}
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} // namespace compiler
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} // namespace internal
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} // namespace v8
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@ -20,11 +20,6 @@ class X64OperandGenerator FINAL : public OperandGenerator {
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Register::ToAllocationIndex(reg));
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}
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InstructionOperand* UseByteRegister(Node* node) {
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// TODO(dcarney): relax constraint.
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return UseFixed(node, rdx);
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}
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InstructionOperand* UseImmediate64(Node* node) { return UseImmediate(node); }
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bool CanBeImmediate(Node* node) {
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@ -59,10 +54,173 @@ class X64OperandGenerator FINAL : public OperandGenerator {
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};
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// Matches nodes of form [x * N] for N in {1,2,4,8}
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class ScaleFactorMatcher : public NodeMatcher {
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public:
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explicit ScaleFactorMatcher(Node* node)
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: NodeMatcher(node), left_(NULL), power_(0) {
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Match();
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}
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bool Matches() { return left_ != NULL; }
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int Power() {
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DCHECK(Matches());
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return power_;
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}
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Node* Left() {
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DCHECK(Matches());
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return left_;
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}
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private:
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void Match() {
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if (opcode() != IrOpcode::kInt32Mul) return;
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Int32BinopMatcher m(node());
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if (!m.right().HasValue()) return;
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int32_t value = m.right().Value();
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switch (value) {
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case 8:
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power_++; // Fall through.
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case 4:
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power_++; // Fall through.
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case 2:
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power_++; // Fall through.
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case 1:
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break;
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default:
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return;
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}
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left_ = m.left().node();
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}
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Node* left_;
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int power_;
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};
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// Matches nodes of form:
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// [x * N]
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// [x * N + K]
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// [x + K]
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// [x] -- fallback case
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// for N in {1,2,4,8} and K int32_t
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class IndexAndDisplacementMatcher : public NodeMatcher {
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public:
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explicit IndexAndDisplacementMatcher(Node* node)
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: NodeMatcher(node), index_node_(node), displacement_(0), power_(0) {
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Match();
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}
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Node* index_node() { return index_node_; }
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int displacement() { return displacement_; }
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int power() { return power_; }
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private:
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void Match() {
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if (opcode() == IrOpcode::kInt32Add) {
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// Assume reduction has put constant on the right.
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Int32BinopMatcher m(node());
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if (m.right().HasValue()) {
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displacement_ = m.right().Value();
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index_node_ = m.left().node();
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}
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}
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// Test scale factor.
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ScaleFactorMatcher scale_matcher(index_node_);
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if (scale_matcher.Matches()) {
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index_node_ = scale_matcher.Left();
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power_ = scale_matcher.Power();
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}
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}
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Node* index_node_;
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int displacement_;
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int power_;
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};
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class AddressingModeMatcher {
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public:
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AddressingModeMatcher(X64OperandGenerator* g, Node* base, Node* index)
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: base_operand_(NULL),
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index_operand_(NULL),
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displacement_operand_(NULL),
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mode_(kMode_None) {
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Int32Matcher index_imm(index);
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if (index_imm.HasValue()) {
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int32_t value = index_imm.Value();
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if (value == 0) {
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mode_ = kMode_MR;
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} else {
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mode_ = kMode_MRI;
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index_operand_ = g->UseImmediate(index);
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}
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base_operand_ = g->UseRegister(base);
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} else {
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// Compute base operand.
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Int64Matcher base_imm(base);
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if (!base_imm.HasValue() || base_imm.Value() != 0) {
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base_operand_ = g->UseRegister(base);
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}
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// Compute index and displacement.
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IndexAndDisplacementMatcher matcher(index);
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index_operand_ = g->UseRegister(matcher.index_node());
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if (matcher.displacement() != 0) {
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displacement_operand_ = g->TempImmediate(matcher.displacement());
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}
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// Compute mode with scale factor one.
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if (base_operand_ == NULL) {
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if (displacement_operand_ == NULL) {
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mode_ = kMode_M1;
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} else {
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mode_ = kMode_M1I;
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}
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} else {
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if (displacement_operand_ == NULL) {
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mode_ = kMode_MR1;
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} else {
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mode_ = kMode_MR1I;
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}
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}
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// Adjust mode to actual scale factor.
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mode_ = GetMode(mode_, matcher.power());
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}
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DCHECK_NE(kMode_None, mode_);
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}
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AddressingMode GetMode(AddressingMode one, int power) {
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return static_cast<AddressingMode>(static_cast<int>(one) + power);
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}
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size_t SetInputs(InstructionOperand** inputs) {
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size_t input_count = 0;
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// Compute inputs_ and input_count.
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if (base_operand_ != NULL) {
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inputs[input_count++] = base_operand_;
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}
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if (index_operand_ != NULL) {
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inputs[input_count++] = index_operand_;
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}
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if (displacement_operand_ != NULL) {
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// Pure displacement mode not supported by x64.
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DCHECK_NE(input_count, 0);
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inputs[input_count++] = displacement_operand_;
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}
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DCHECK_NE(input_count, 0);
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return input_count;
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}
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static const int kMaxInputCount = 3;
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InstructionOperand* base_operand_;
|
||||
InstructionOperand* index_operand_;
|
||||
InstructionOperand* displacement_operand_;
|
||||
AddressingMode mode_;
|
||||
};
|
||||
|
||||
|
||||
void InstructionSelector::VisitLoad(Node* node) {
|
||||
MachineType rep = RepresentationOf(OpParameter<LoadRepresentation>(node));
|
||||
MachineType typ = TypeOf(OpParameter<LoadRepresentation>(node));
|
||||
X64OperandGenerator g(this);
|
||||
Node* base = node->InputAt(0);
|
||||
Node* index = node->InputAt(1);
|
||||
|
||||
@ -93,18 +251,14 @@ void InstructionSelector::VisitLoad(Node* node) {
|
||||
UNREACHABLE();
|
||||
return;
|
||||
}
|
||||
if (g.CanBeImmediate(base)) {
|
||||
// load [#base + %index]
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MRI),
|
||||
g.DefineAsRegister(node), g.UseRegister(index), g.UseImmediate(base));
|
||||
} else if (g.CanBeImmediate(index)) { // load [%base + #index]
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MRI),
|
||||
g.DefineAsRegister(node), g.UseRegister(base), g.UseImmediate(index));
|
||||
} else { // load [%base + %index + K]
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MR1I),
|
||||
g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
|
||||
}
|
||||
// TODO(turbofan): addressing modes [r+r*{2,4,8}+K]
|
||||
|
||||
X64OperandGenerator g(this);
|
||||
AddressingModeMatcher matcher(&g, base, index);
|
||||
InstructionCode code = opcode | AddressingModeField::encode(matcher.mode_);
|
||||
InstructionOperand* outputs[] = {g.DefineAsRegister(node)};
|
||||
InstructionOperand* inputs[AddressingModeMatcher::kMaxInputCount];
|
||||
int input_count = matcher.SetInputs(inputs);
|
||||
Emit(code, 1, outputs, input_count, inputs);
|
||||
}
|
||||
|
||||
|
||||
@ -128,14 +282,6 @@ void InstructionSelector::VisitStore(Node* node) {
|
||||
return;
|
||||
}
|
||||
DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind());
|
||||
InstructionOperand* val;
|
||||
if (g.CanBeImmediate(value)) {
|
||||
val = g.UseImmediate(value);
|
||||
} else if (rep == kRepWord8 || rep == kRepBit) {
|
||||
val = g.UseByteRegister(value);
|
||||
} else {
|
||||
val = g.UseRegister(value);
|
||||
}
|
||||
ArchOpcode opcode;
|
||||
switch (rep) {
|
||||
case kRepFloat32:
|
||||
@ -162,18 +308,20 @@ void InstructionSelector::VisitStore(Node* node) {
|
||||
UNREACHABLE();
|
||||
return;
|
||||
}
|
||||
if (g.CanBeImmediate(base)) {
|
||||
// store [#base + %index], %|#value
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MRI), NULL,
|
||||
g.UseRegister(index), g.UseImmediate(base), val);
|
||||
} else if (g.CanBeImmediate(index)) { // store [%base + #index], %|#value
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MRI), NULL,
|
||||
g.UseRegister(base), g.UseImmediate(index), val);
|
||||
} else { // store [%base + %index], %|#value
|
||||
Emit(opcode | AddressingModeField::encode(kMode_MR1I), NULL,
|
||||
g.UseRegister(base), g.UseRegister(index), val);
|
||||
|
||||
InstructionOperand* val;
|
||||
if (g.CanBeImmediate(value)) {
|
||||
val = g.UseImmediate(value);
|
||||
} else {
|
||||
val = g.UseRegister(value);
|
||||
}
|
||||
// TODO(turbofan): addressing modes [r+r*{2,4,8}+K]
|
||||
|
||||
AddressingModeMatcher matcher(&g, base, index);
|
||||
InstructionCode code = opcode | AddressingModeField::encode(matcher.mode_);
|
||||
InstructionOperand* inputs[AddressingModeMatcher::kMaxInputCount + 1];
|
||||
int input_count = matcher.SetInputs(inputs);
|
||||
inputs[input_count++] = val;
|
||||
Emit(code, 0, static_cast<InstructionOperand**>(NULL), input_count, inputs);
|
||||
}
|
||||
|
||||
|
||||
@ -702,8 +850,6 @@ void InstructionSelector::VisitCall(Node* call, BasicBlock* continuation,
|
||||
// Compute InstructionOperands for inputs and outputs.
|
||||
InitializeCallBuffer(call, &buffer, true, true);
|
||||
|
||||
// TODO(dcarney): stack alignment for c calls.
|
||||
// TODO(dcarney): shadow space on window for c calls.
|
||||
// Push any stack arguments.
|
||||
for (NodeVectorRIter input = buffer.pushed_nodes.rbegin();
|
||||
input != buffer.pushed_nodes.rend(); input++) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user