[wasm] add simd horiz and reduce to interpreter
This CL adds simd select, addHoriz, shuffle, anyTrue and all true to the interpreter. It also gets rid of SIMD_COMPILED_AND_LOWERED_TEST and SIMD_COMPILED_TEST macros. R=gdeepti@chromium.org BUG=v8:6020 Change-Id: I44abbcaddc3223a95c79ccc65ae9c6bf1a911c5d Reviewed-on: https://chromium-review.googlesource.com/1119258 Commit-Queue: Aseem Garg <aseemgarg@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#54116}
This commit is contained in:
Aseem Garg
Commit Bot
parent
90da229fa2
commit
d3fe5ac7c3
@ -1160,6 +1160,7 @@ class WasmDecoder : public Decoder {
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FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(DECLARE_OPCODE_CASE)
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return {1, 1};
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FOREACH_SIMD_1_OPERAND_2_PARAM_OPCODE(DECLARE_OPCODE_CASE)
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FOREACH_SIMD_MASK_OPERAND_OPCODE(DECLARE_OPCODE_CASE)
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return {2, 1};
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default: {
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sig = WasmOpcodes::Signature(opcode);
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@ -1917,6 +1917,67 @@ class ThreadImpl {
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PACK_CASE(I8x16UConvertI16x8, int8, i16x8, int16, 16, uint8_t, int8_t,
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true)
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#undef PACK_CASE
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case kExprS128Select: {
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int4 v2 = Pop().to_s128().to_i32x4();
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int4 v1 = Pop().to_s128().to_i32x4();
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int4 bool_val = Pop().to_s128().to_i32x4();
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int4 res;
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for (size_t i = 0; i < 4; ++i) {
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res.val[i] = v2.val[i] ^ ((v1.val[i] ^ v2.val[i]) & bool_val.val[i]);
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}
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Push(WasmValue(Simd128(res)));
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return true;
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}
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#define ADD_HORIZ_CASE(op, name, stype, count) \
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case kExpr##op: { \
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WasmValue v2 = Pop(); \
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WasmValue v1 = Pop(); \
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stype s1 = v1.to_s128().to_##name(); \
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stype s2 = v2.to_s128().to_##name(); \
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stype res; \
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for (size_t i = 0; i < count / 2; ++i) { \
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res.val[i] = s1.val[i * 2] + s1.val[i * 2 + 1]; \
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res.val[i + count / 2] = s2.val[i * 2] + s2.val[i * 2 + 1]; \
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} \
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Push(WasmValue(Simd128(res))); \
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return true; \
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}
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ADD_HORIZ_CASE(I32x4AddHoriz, i32x4, int4, 4)
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ADD_HORIZ_CASE(F32x4AddHoriz, f32x4, float4, 4)
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ADD_HORIZ_CASE(I16x8AddHoriz, i16x8, int8, 8)
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#undef ADD_HORIZ_CASE
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case kExprS8x16Shuffle: {
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Simd8x16ShuffleImmediate<Decoder::kNoValidate> imm(decoder,
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code->at(pc));
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len += 16;
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int16 v2 = Pop().to_s128().to_i8x16();
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int16 v1 = Pop().to_s128().to_i8x16();
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int16 res;
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for (size_t i = 0; i < kSimd128Size; ++i) {
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int lane = imm.shuffle[i];
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res.val[i] =
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lane < kSimd128Size ? v1.val[lane] : v2.val[lane - kSimd128Size];
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}
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Push(WasmValue(Simd128(res)));
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return true;
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}
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#define REDUCTION_CASE(op, name, stype, count, operation) \
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case kExpr##op: { \
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stype s = Pop().to_s128().to_##name(); \
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int32_t res = s.val[0]; \
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for (size_t i = 1; i < count; ++i) { \
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res = res operation static_cast<int32_t>(s.val[i]); \
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} \
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Push(WasmValue(res)); \
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return true; \
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}
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REDUCTION_CASE(S1x4AnyTrue, i32x4, int4, 4, |)
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REDUCTION_CASE(S1x4AllTrue, i32x4, int4, 4, &)
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REDUCTION_CASE(S1x8AnyTrue, i16x8, int8, 8, |)
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REDUCTION_CASE(S1x8AllTrue, i16x8, int8, 8, &)
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REDUCTION_CASE(S1x16AnyTrue, i8x16, int16, 16, |)
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REDUCTION_CASE(S1x16AllTrue, i8x16, int16, 16, &)
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#undef REDUCTION_CASE
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default:
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return false;
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}
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@ -416,6 +416,41 @@
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'test-run-wasm-simd/RunWasm_SimdLoadStoreLoad_simd_turbofan': [SKIP],
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'test-run-wasm-simd/RunWasm_SimdLoadStoreLoad_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_SimdLoadStoreLoad_simd_lowered': [SKIP],
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'test-run-wasm-simd/RunWasm_I32x4AddHoriz_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_I16x8AddHoriz_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_F32x4AddHoriz_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4Dup_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4ZipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4ZipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4UnzipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4UnzipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4TransposeLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4TransposeRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x2Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S32x4Irregular_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8Dup_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8ZipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8ZipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8UnzipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8UnzipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8TransposeLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8TransposeRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x4Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x2Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S16x8Irregular_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16Dup_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16ZipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16ZipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16UnzipLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16UnzipRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16TransposeLeft_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16TransposeRight_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x8Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x4Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x2Reverse_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16Irregular_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16Blend_interpreter': [SKIP],
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'test-run-wasm-simd/RunWasm_S8x16Concat_interpreter': [SKIP],
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}], # 'arch == mips or arch == mips64'
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@ -49,30 +49,6 @@ typedef int8_t (*Int8ShiftOp)(int8_t, int);
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void RunWasm_##name##_Impl(LowerSimd lower_simd, \
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WasmExecutionMode execution_mode)
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#define WASM_SIMD_COMPILED_AND_LOWERED_TEST(name) \
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void RunWasm_##name##_Impl(LowerSimd lower_simd, \
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WasmExecutionMode execution_mode); \
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TEST(RunWasm_##name##_turbofan) { \
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EXPERIMENTAL_FLAG_SCOPE(simd); \
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RunWasm_##name##_Impl(kNoLowerSimd, kExecuteTurbofan); \
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} \
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TEST(RunWasm_##name##_simd_lowered) { \
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EXPERIMENTAL_FLAG_SCOPE(simd); \
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RunWasm_##name##_Impl(kLowerSimd, kExecuteTurbofan); \
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} \
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void RunWasm_##name##_Impl(LowerSimd lower_simd, \
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WasmExecutionMode execution_mode)
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#define WASM_SIMD_COMPILED_TEST(name) \
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void RunWasm_##name##_Impl(LowerSimd lower_simd, \
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WasmExecutionMode execution_mode); \
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TEST(RunWasm_##name##_turbofan) { \
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EXPERIMENTAL_FLAG_SCOPE(simd); \
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RunWasm_##name##_Impl(kNoLowerSimd, kExecuteTurbofan); \
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} \
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void RunWasm_##name##_Impl(LowerSimd lower_simd, \
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WasmExecutionMode execution_mode)
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// Generic expected value functions.
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template <typename T>
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T Negate(T a) {
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@ -1630,7 +1606,7 @@ WASM_SIMD_TEST(I8x16ShrU) {
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// rest false, and comparing for non-equality with zero to convert to a boolean
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// vector.
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#define WASM_SIMD_SELECT_TEST(format) \
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S##format##Select) { \
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WASM_SIMD_TEST(S##format##Select) { \
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WasmRunner<int32_t, int32_t, int32_t> r(execution_mode, lower_simd); \
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byte val1 = 0; \
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byte val2 = 1; \
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@ -1670,7 +1646,7 @@ WASM_SIMD_SELECT_TEST(8x16)
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// Test Select by making a mask where the 0th and 3rd lanes are non-zero and the
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// rest 0. The mask is not the result of a comparison op.
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#define WASM_SIMD_NON_CANONICAL_SELECT_TEST(format) \
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S##format##NonCanonicalSelect) { \
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WASM_SIMD_TEST(S##format##NonCanonicalSelect) { \
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WasmRunner<int32_t, int32_t, int32_t, int32_t> r(execution_mode, \
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lower_simd); \
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byte val1 = 0; \
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@ -1738,17 +1714,17 @@ void RunBinaryLaneOpTest(
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}
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(I32x4AddHoriz) {
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WASM_SIMD_TEST(I32x4AddHoriz) {
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RunBinaryLaneOpTest<int32_t>(execution_mode, lower_simd, kExprI32x4AddHoriz,
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{{1, 5, 9, 13}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(I16x8AddHoriz) {
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WASM_SIMD_TEST(I16x8AddHoriz) {
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RunBinaryLaneOpTest<int16_t>(execution_mode, lower_simd, kExprI16x8AddHoriz,
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{{1, 5, 9, 13, 17, 21, 25, 29}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(F32x4AddHoriz) {
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WASM_SIMD_TEST(F32x4AddHoriz) {
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RunBinaryLaneOpTest<float>(execution_mode, lower_simd, kExprF32x4AddHoriz,
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{{1.0f, 5.0f, 9.0f, 13.0f}});
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}
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@ -1780,191 +1756,191 @@ void RunShuffleOpTest(WasmExecutionMode execution_mode, LowerSimd lower_simd,
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#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
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V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
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// Test some regular shuffles that may have special handling on some targets.
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4Dup) {
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WASM_SIMD_TEST(S32x4Dup) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{16, 17, 18, 19, 16, 17, 18, 19, 16, 17, 18, 19, 16, 17, 18, 19}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4ZipLeft) {
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WASM_SIMD_TEST(S32x4ZipLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4ZipRight) {
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WASM_SIMD_TEST(S32x4ZipRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4UnzipLeft) {
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WASM_SIMD_TEST(S32x4UnzipLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4UnzipRight) {
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WASM_SIMD_TEST(S32x4UnzipRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4TransposeLeft) {
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WASM_SIMD_TEST(S32x4TransposeLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4TransposeRight) {
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WASM_SIMD_TEST(S32x4TransposeRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31}});
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}
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// Reverses are only unary.
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x2Reverse) {
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WASM_SIMD_TEST(S32x2Reverse) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11}});
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}
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// Test irregular shuffle.
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S32x4Irregular) {
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WASM_SIMD_TEST(S32x4Irregular) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 2, 3, 16, 17, 18, 19, 16, 17, 18, 19, 20, 21, 22, 23}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8Dup) {
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WASM_SIMD_TEST(S16x8Dup) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19, 18, 19}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8ZipLeft) {
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WASM_SIMD_TEST(S16x8ZipLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8ZipRight) {
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WASM_SIMD_TEST(S16x8ZipRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8UnzipLeft) {
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WASM_SIMD_TEST(S16x8UnzipLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8UnzipRight) {
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WASM_SIMD_TEST(S16x8UnzipRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8TransposeLeft) {
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WASM_SIMD_TEST(S16x8TransposeLeft) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{0, 1, 16, 17, 4, 5, 20, 21, 8, 9, 24, 25, 12, 13, 28, 29}});
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}
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8TransposeRight) {
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WASM_SIMD_TEST(S16x8TransposeRight) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
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{{2, 3, 18, 19, 6, 7, 22, 23, 10, 11, 26, 27, 14, 15, 30, 31}});
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}
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// TODO(simd) 'Reverse' tests should be 2-operand shuffles, not swizzles.
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WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x4Reverse) {
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WASM_SIMD_TEST(S16x4Reverse) {
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RunShuffleOpTest<int8_t>(
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execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x2Reverse) {
|
||||
WASM_SIMD_TEST(S16x2Reverse) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S16x8Irregular) {
|
||||
WASM_SIMD_TEST(S16x8Irregular) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{0, 1, 16, 17, 16, 17, 0, 1, 4, 5, 20, 21, 6, 7, 22, 23}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Dup) {
|
||||
WASM_SIMD_TEST(S8x16Dup) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16ZipLeft) {
|
||||
WASM_SIMD_TEST(S8x16ZipLeft) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16ZipRight) {
|
||||
WASM_SIMD_TEST(S8x16ZipRight) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16UnzipLeft) {
|
||||
WASM_SIMD_TEST(S8x16UnzipLeft) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16UnzipRight) {
|
||||
WASM_SIMD_TEST(S8x16UnzipRight) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16TransposeLeft) {
|
||||
WASM_SIMD_TEST(S8x16TransposeLeft) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16TransposeRight) {
|
||||
WASM_SIMD_TEST(S8x16TransposeRight) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x8Reverse) {
|
||||
WASM_SIMD_TEST(S8x8Reverse) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x4Reverse) {
|
||||
WASM_SIMD_TEST(S8x4Reverse) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x2Reverse) {
|
||||
WASM_SIMD_TEST(S8x2Reverse) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}});
|
||||
}
|
||||
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Irregular) {
|
||||
WASM_SIMD_TEST(S8x16Irregular) {
|
||||
RunShuffleOpTest<int8_t>(
|
||||
execution_mode, lower_simd, kExprS8x16Shuffle,
|
||||
{{0, 16, 0, 16, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}});
|
||||
}
|
||||
|
||||
// Test shuffles that blend the two vectors (elements remain in their lanes.)
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Blend) {
|
||||
WASM_SIMD_TEST(S8x16Blend) {
|
||||
static const int kLanes = 16;
|
||||
std::array<uint8_t, kLanes> expected;
|
||||
for (int bias = 1; bias < kLanes; bias++) {
|
||||
@ -1975,7 +1951,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Blend) {
|
||||
}
|
||||
|
||||
// Test shuffles that concatenate the two vectors.
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Concat) {
|
||||
WASM_SIMD_TEST(S8x16Concat) {
|
||||
static const int kLanes = 16;
|
||||
std::array<uint8_t, kLanes> expected;
|
||||
// n is offset or bias of concatenation.
|
||||
@ -1997,7 +1973,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(S8x16Concat) {
|
||||
// result. Use relational ops on numeric vectors to create the boolean vector
|
||||
// test inputs. Test inputs with all true, all false, one true, and one false.
|
||||
#define WASM_SIMD_BOOL_REDUCTION_TEST(format, lanes) \
|
||||
WASM_SIMD_COMPILED_AND_LOWERED_TEST(ReductionTest##lanes) { \
|
||||
WASM_SIMD_TEST(ReductionTest##lanes) { \
|
||||
WasmRunner<int32_t> r(execution_mode, lower_simd); \
|
||||
byte zero = r.AllocateLocal(kWasmS128); \
|
||||
byte one_one = r.AllocateLocal(kWasmS128); \
|
||||
@ -2338,8 +2314,6 @@ WASM_SIMD_TEST(SimdLoadStoreLoad) {
|
||||
}
|
||||
|
||||
#undef WASM_SIMD_TEST
|
||||
#undef WASM_SIMD_COMPILED_AND_LOWERED_TEST
|
||||
#undef WASM_SIMD_COMPILED_TEST
|
||||
#undef WASM_SIMD_CHECK_LANE
|
||||
#undef WASM_SIMD_CHECK4
|
||||
#undef WASM_SIMD_CHECK_SPLAT4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user