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[riscv64] skip rvv test when no rvv

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Change-Id: If9619a796865b402361f521c0529e8452a9a3078
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3343862
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#78403}
This commit is contained in:
Lu Yahan 2021-12-16 17:22:34 +08:00 committed by V8 LUCI CQ
parent c042c390a1
commit d42e4f6e8d
1 changed files with 10 additions and 0 deletions
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10
test/cctest/test-assembler-riscv64.cc
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@ -1979,6 +1979,7 @@ TEST(li_estimate) {
#define UTEST_LOAD_STORE_RVV(ldname, stname, SEW, arg...) \
TEST(RISCV_UTEST_##stname##ldname##SEW) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
Isolate* isolate = CcTest::i_isolate(); \
HandleScope scope(isolate); \
@ -1998,6 +1999,8 @@ UTEST_LOAD_STORE_RVV(vl, vs, E8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
// UTEST_LOAD_STORE_RVV(vl, vs, E8, 127, 127, 127, 127, 127, 127, 127)
TEST(RVV_VSETIVLI) {
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
@ -2009,6 +2012,8 @@ TEST(RVV_VSETIVLI) {
}
TEST(RVV_VFMV) {
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
@ -2036,6 +2041,7 @@ inline int32_t ToImm5(int32_t v) {
// Tests for vector integer arithmetic instructions between vector and vector
#define UTEST_RVV_VI_VV_FORM_WITH_RES(instr_name, width, array, expect_res) \
TEST(RISCV_UTEST_##instr_name##_##width) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
auto fn = [](MacroAssembler& assm) { \
__ VU.set(t0, VSew::E##width, Vlmul::m1); \
@ -2055,6 +2061,7 @@ inline int32_t ToImm5(int32_t v) {
// Tests for vector integer arithmetic instructions between vector and scalar
#define UTEST_RVV_VI_VX_FORM_WITH_RES(instr_name, width, array, expect_res) \
TEST(RISCV_UTEST_##instr_name##_##width) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
auto fn = [](MacroAssembler& assm) { \
__ VU.set(t0, VSew::E##width, Vlmul::m1); \
@ -2074,6 +2081,7 @@ inline int32_t ToImm5(int32_t v) {
// immediate
#define UTEST_RVV_VI_VI_FORM_WITH_RES(instr_name, width, array, expect_res) \
TEST(RISCV_UTEST_##instr_name##_##width) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
for (int##width##_t rs1_val : array) { \
for (int##width##_t rs2_val : array) { \
@ -2183,6 +2191,7 @@ UTEST_RVV_VI_VX_FORM_WITH_FN(vminu_vx, 32, ARRAY_INT32, std::min<uint32_t>)
// vector and vector
#define UTEST_RVV_VF_VV_FORM_WITH_RES(instr_name, array, expect_res) \
TEST(RISCV_UTEST_##instr_name) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
auto fn = [](MacroAssembler& assm) { \
__ VU.set(t0, VSew::E32, Vlmul::m1); \
@ -2203,6 +2212,7 @@ UTEST_RVV_VI_VX_FORM_WITH_FN(vminu_vx, 32, ARRAY_INT32, std::min<uint32_t>)
// vector and scalar
#define UTEST_RVV_VF_VF_FORM_WITH_RES(instr_name, array, expect_res) \
TEST(RISCV_UTEST_##instr_name) { \
if (!CpuFeatures::IsSupported(RISCV_SIMD)) return; \
CcTest::InitializeVM(); \
auto fn = [](MacroAssembler& assm) { \
__ VU.set(t0, VSew::E32, Vlmul::m1); \