[wasm-simd][ia32] Implement saturating rounding multiply high
Implementation is the same as x64. Disassembly support for the new instruction, pmulhrsw, is already supported due to the macro list. Bug: v8:10971 Change-Id: I099c4f8c3da521006ef5e2b151626f25a5df1ed9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2620898 Reviewed-by: Bill Budge <bbudge@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#72021}
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@ -527,6 +527,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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AVX_OP3_XO_SSE4(Pmaxsd, pmaxsd)
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AVX_OP3_WITH_TYPE_SCOPE(Pmaddubsw, pmaddubsw, XMMRegister, XMMRegister, SSSE3)
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AVX_OP3_WITH_TYPE_SCOPE(Pmulhrsw, pmulhrsw, XMMRegister, XMMRegister, SSSE3)
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#undef AVX_OP3_XO_SSE4
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#undef AVX_OP3_WITH_TYPE_SCOPE
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@ -70,7 +70,8 @@
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V(pmaddubsw, 66, 0F, 38, 04) \
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V(psignb, 66, 0F, 38, 08) \
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V(psignw, 66, 0F, 38, 09) \
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V(psignd, 66, 0F, 38, 0A)
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V(psignd, 66, 0F, 38, 0A) \
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V(pmulhrsw, 66, 0F, 38, 0B)
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// SSSE3 instructions whose AVX version has two operands.
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#define SSSE3_UNOP_INSTRUCTION_LIST(V) \
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@ -2328,6 +2328,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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__ Pmaddubsw(dst, i.InputSimd128Register(0), kScratchDoubleReg);
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break;
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}
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case kIA32I16x8Q15MulRSatS: {
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XMMRegister dst = i.OutputSimd128Register();
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XMMRegister src0 = i.InputSimd128Register(0);
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XMMRegister src1 = i.InputSimd128Register(1);
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// k = i16x8.splat(0x8000)
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__ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
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__ Psllw(kScratchDoubleReg, kScratchDoubleReg, byte{15});
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__ Pmulhrsw(dst, src0, src1);
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__ Pcmpeqw(kScratchDoubleReg, dst);
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__ Pxor(dst, kScratchDoubleReg);
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break;
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}
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case kIA32I32x4SignSelect: {
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ASSEMBLE_SIMD_SIGN_SELECT(blendvps);
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break;
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@ -297,6 +297,7 @@ namespace compiler {
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V(IA32I16x8ExtMulHighI8x16U) \
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V(IA32I16x8ExtAddPairwiseI8x16S) \
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V(IA32I16x8ExtAddPairwiseI8x16U) \
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V(IA32I16x8Q15MulRSatS) \
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V(IA32I8x16Splat) \
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V(IA32I8x16ExtractLaneS) \
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V(IA32Pinsrb) \
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@ -279,6 +279,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kIA32I16x8ExtMulHighI8x16U:
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case kIA32I16x8ExtAddPairwiseI8x16S:
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case kIA32I16x8ExtAddPairwiseI8x16U:
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case kIA32I16x8Q15MulRSatS:
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case kIA32I8x16Splat:
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case kIA32I8x16ExtractLaneS:
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case kIA32Pinsrb:
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@ -2256,6 +2256,7 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
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V(I16x8ExtMulHighI8x16S) \
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V(I16x8ExtMulLowI8x16U) \
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V(I16x8ExtMulHighI8x16U) \
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V(I16x8Q15MulRSatS) \
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V(I8x16RoundingAverageU)
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#define SIMD_UNOP_LIST(V) \
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@ -2748,10 +2748,12 @@ void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
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// && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM
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// && !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_MIPS
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#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
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#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32
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// TODO(v8:10971) Prototype i16x8.q15mulr_sat_s
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void InstructionSelector::VisitI16x8Q15MulRSatS(Node* node) { UNIMPLEMENTED(); }
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#endif // !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32
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#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
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// TODO(v8:10972) Prototype i64x2 widen i32x4.
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void InstructionSelector::VisitI64x2SConvertI32x4Low(Node* node) {
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UNIMPLEMENTED();
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@ -2328,14 +2328,14 @@ WASM_SIMD_TEST(I16x8RoundingAverageU) {
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base::RoundingAverageUnsigned);
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}
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#if V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
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#if V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32
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// TODO(v8:10971) Prototype i16x8.q15mulr_sat_s
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WASM_SIMD_TEST_NO_LOWERING(I16x8Q15MulRSatS) {
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FLAG_SCOPE(wasm_simd_post_mvp);
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RunI16x8BinOpTest<int16_t>(execution_tier, lower_simd, kExprI16x8Q15MulRSatS,
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SaturateRoundingQMul<int16_t>);
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}
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#endif // V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
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#endif // V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32
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namespace {
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enum class MulHalf { kLow, kHigh };
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