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MIPS64 Correct LLD and SCD implementation in simulator.

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Change-Id: I18300c788d1a0eecb280e4cac72e52db81dd681d
Reviewed-on: https://chromium-review.googlesource.com/c/1322452
Reviewed-by: Ivica Bogosavljevic <ibogosavljevic@wavecomp.com>
Commit-Queue: Ivica Bogosavljevic <ibogosavljevic@wavecomp.com>
Cr-Commit-Position: refs/heads/master@{#57313}
This commit is contained in:
Predrag Rudic 2018-11-07 10:28:56 +01:00 committed by Commit Bot
parent 47764c761f
commit d684678713
1 changed files with 4 additions and 4 deletions
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8
src/mips64/simulator-mips64.cc
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@ -7041,13 +7041,13 @@ void Simulator::DecodeTypeImmediate() {
case LLD: {
// LL/SC sequence cannot be simulated properly
DCHECK_EQ(kArchVariant, kMips64r2);
set_register(rt_reg, ReadD(rs + se_imm16, instr_.instr()));
set_register(rt_reg, Read2W(rs + se_imm16, instr_.instr()));
break;
}
case SCD: {
// LL/SC sequence cannot be simulated properly
DCHECK_EQ(kArchVariant, kMips64r2);
WriteD(rs + se_imm16, rt, instr_.instr());
Write2W(rs + se_imm16, rt, instr_.instr());
set_register(rt_reg, 1);
break;
}
@ -7149,7 +7149,7 @@ void Simulator::DecodeTypeImmediate() {
DCHECK_EQ(kArchVariant, kMips64r6);
int64_t base = get_register(instr_.BaseValue());
int32_t offset9 = instr_.Imm9Value();
set_register(rt_reg, ReadD(base + offset9, instr_.instr()));
set_register(rt_reg, Read2W(base + offset9, instr_.instr()));
break;
}
case SC_R6: {
@ -7166,7 +7166,7 @@ void Simulator::DecodeTypeImmediate() {
DCHECK_EQ(kArchVariant, kMips64r6);
int64_t base = get_register(instr_.BaseValue());
int32_t offset9 = instr_.Imm9Value();
WriteD(base + offset9, rt, instr_.instr());
Write2W(base + offset9, rt, instr_.instr());
set_register(rt_reg, 1);
break;
}