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Fix a warning about inline asm source/destination mismatches for cache_type_register_.

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The warning notes that we'd want a 'w' register here because the size of
the operand is 32-bit, however, the instruction only takes an 'x'
register and so force that using the 'x' modifier on the instruction.

BUG=

Review URL: https://codereview.chromium.org/1817963003

Cr-Commit-Position: refs/heads/master@{#35008}
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echristo 2016-03-22 14:47:38 -07:00 committed by Commit bot
parent 4e8670d1fa
commit d6d8230697
1 changed files with 1 additions and 1 deletions
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src/arm64/cpu-arm64.cc
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@ -19,7 +19,7 @@ class CacheLineSizes {
cache_type_register_ = 0; cache_type_register_ = 0;
#else #else
// Copy the content of the cache type register to a core register. // Copy the content of the cache type register to a core register.
__asm__ __volatile__("mrs %[ctr], ctr_el0" // NOLINT __asm__ __volatile__("mrs %x[ctr], ctr_el0" // NOLINT
: [ctr] "=r"(cache_type_register_)); : [ctr] "=r"(cache_type_register_));
#endif #endif
} }