C++20 fixes.
Math between disparate enums is deprecated. Use constexprs instead. This requires switching some caller code to work with the new non-enum constants also. Bug: chromium:1284275 Change-Id: Ifb3c8757ed62e2a0966120f830f0a7e282b53a16 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3661148 Auto-Submit: Peter Kasting <pkasting@chromium.org> Commit-Queue: Leszek Swirski <leszeks@chromium.org> Reviewed-by: Leszek Swirski <leszeks@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Peter Kasting <pkasting@chromium.org> Cr-Commit-Position: refs/heads/main@{#80722}
This commit is contained in:
Peter Kasting
V8 LUCI CQ
parent
1f413298e4
commit
db24d136fb
@ -4388,9 +4388,9 @@ enum IntegerBinOp {
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VQRDMULH
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};
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static Instr EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt,
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QwNeonRegister dst, QwNeonRegister src1,
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QwNeonRegister src2) {
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static Instr EncodeNeonDataTypeBinOp(IntegerBinOp op, NeonDataType dt,
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QwNeonRegister dst, QwNeonRegister src1,
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QwNeonRegister src2) {
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int op_encoding = 0;
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switch (op) {
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case VADD:
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@ -4447,11 +4447,13 @@ static Instr EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt,
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n * B7 | B6 | m * B5 | vm | op_encoding;
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}
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static Instr EncodeNeonBinOp(IntegerBinOp op, NeonSize size, QwNeonRegister dst,
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QwNeonRegister src1, QwNeonRegister src2) {
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static Instr EncodeNeonSizeBinOp(IntegerBinOp op, NeonSize size,
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QwNeonRegister dst, QwNeonRegister src1,
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QwNeonRegister src2) {
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// Map NeonSize values to the signed values in NeonDataType, so the U bit
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// will be 0.
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return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
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return EncodeNeonDataTypeBinOp(op, static_cast<NeonDataType>(size), dst, src1,
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src2);
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}
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void Assembler::vadd(QwNeonRegister dst, QwNeonRegister src1,
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@ -4467,7 +4469,7 @@ void Assembler::vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vadd(Qn, Qm) SIMD integer addition.
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// Instruction details available in ARM DDI 0406C.b, A8-828.
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emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
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emit(EncodeNeonSizeBinOp(VADD, size, dst, src1, src2));
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}
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void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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@ -4475,7 +4477,7 @@ void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vqadd(Qn, Qm) SIMD integer saturating addition.
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// Instruction details available in ARM DDI 0406C.b, A8-996.
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emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VQADD, dt, dst, src1, src2));
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}
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void Assembler::vsub(QwNeonRegister dst, QwNeonRegister src1,
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@ -4491,7 +4493,7 @@ void Assembler::vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vsub(Qn, Qm) SIMD integer subtraction.
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// Instruction details available in ARM DDI 0406C.b, A8-1084.
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emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
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emit(EncodeNeonSizeBinOp(VSUB, size, dst, src1, src2));
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}
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void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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@ -4499,7 +4501,7 @@ void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vqsub(Qn, Qm) SIMD integer saturating subtraction.
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// Instruction details available in ARM DDI 0406C.b, A8-1020.
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emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VQSUB, dt, dst, src1, src2));
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}
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void Assembler::vmlal(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
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@ -4534,7 +4536,7 @@ void Assembler::vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vadd(Qn, Qm) SIMD integer multiply.
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// Instruction details available in ARM DDI 0406C.b, A8-960.
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emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
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emit(EncodeNeonSizeBinOp(VMUL, size, dst, src1, src2));
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}
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void Assembler::vmull(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
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@ -4567,7 +4569,7 @@ void Assembler::vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vmin(Qn, Qm) SIMD integer MIN.
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// Instruction details available in ARM DDI 0406C.b, A8-926.
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emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VMIN, dt, dst, src1, src2));
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}
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void Assembler::vmax(QwNeonRegister dst, QwNeonRegister src1,
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@ -4583,7 +4585,7 @@ void Assembler::vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vmax(Qn, Qm) SIMD integer MAX.
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// Instruction details available in ARM DDI 0406C.b, A8-926.
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emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VMAX, dt, dst, src1, src2));
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}
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enum NeonShiftOp { VSHL, VSHR, VSLI, VSRI, VSRA };
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@ -4860,7 +4862,7 @@ void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vtst(Qn, Qm) SIMD test integer operands.
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// Instruction details available in ARM DDI 0406C.b, A8-1098.
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emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
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emit(EncodeNeonSizeBinOp(VTST, size, dst, src1, src2));
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}
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void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1,
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@ -4876,7 +4878,7 @@ void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vceq(Qn, Qm) SIMD integer compare equal.
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// Instruction details available in ARM DDI 0406C.b, A8-844.
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emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
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emit(EncodeNeonSizeBinOp(VCEQ, size, dst, src1, src2));
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}
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void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
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@ -4901,7 +4903,7 @@ void Assembler::vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vcge(Qn, Qm) SIMD integer compare greater or equal.
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// Instruction details available in ARM DDI 0406C.b, A8-848.
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emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VCGE, dt, dst, src1, src2));
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}
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void Assembler::vcgt(QwNeonRegister dst, QwNeonRegister src1,
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@ -4917,7 +4919,7 @@ void Assembler::vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vcgt(Qn, Qm) SIMD integer compare greater than.
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// Instruction details available in ARM DDI 0406C.b, A8-852.
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emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VCGT, dt, dst, src1, src2));
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}
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void Assembler::vclt(NeonSize size, QwNeonRegister dst, QwNeonRegister src,
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@ -4934,7 +4936,7 @@ void Assembler::vrhadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
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DCHECK(IsEnabled(NEON));
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// Qd = vrhadd(Qn, Qm) SIMD integer rounding halving add.
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// Instruction details available in ARM DDI 0406C.b, A8-1030.
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emit(EncodeNeonBinOp(VRHADD, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VRHADD, dt, dst, src1, src2));
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}
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void Assembler::vext(QwNeonRegister dst, QwNeonRegister src1,
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@ -5044,7 +5046,7 @@ void Assembler::vqrdmulh(NeonDataType dt, QwNeonRegister dst,
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QwNeonRegister src1, QwNeonRegister src2) {
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DCHECK(IsEnabled(NEON));
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DCHECK(dt == NeonS16 || dt == NeonS32);
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emit(EncodeNeonBinOp(VQRDMULH, dt, dst, src1, src2));
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emit(EncodeNeonDataTypeBinOp(VQRDMULH, dt, dst, src1, src2));
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}
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void Assembler::vcnt(QwNeonRegister dst, QwNeonRegister src) {
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@ -60,6 +60,10 @@ constexpr int kVldrMaxReachBits = 10;
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// is still addressable with a single load instruction.
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constexpr int kRootRegisterBias = 4095;
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// TODO(pkasting): For all the enum type aliases below, if overload resolution
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// is desired, we could try to add some kind of constexpr class with implicit
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// conversion to/from int and operator overloads, then inherit from that.
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// -----------------------------------------------------------------------------
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// Conditions.
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@ -73,32 +77,32 @@ constexpr int kRootRegisterBias = 4095;
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// General constants are in an anonymous enum in class Instr.
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// Values for the condition field as defined in section A3.2
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enum Condition {
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kNoCondition = -1,
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using Condition = int;
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constexpr Condition kNoCondition = -1;
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eq = 0 << 28, // Z set Equal.
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ne = 1 << 28, // Z clear Not equal.
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cs = 2 << 28, // C set Unsigned higher or same.
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cc = 3 << 28, // C clear Unsigned lower.
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mi = 4 << 28, // N set Negative.
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pl = 5 << 28, // N clear Positive or zero.
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vs = 6 << 28, // V set Overflow.
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vc = 7 << 28, // V clear No overflow.
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hi = 8 << 28, // C set, Z clear Unsigned higher.
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ls = 9 << 28, // C clear or Z set Unsigned lower or same.
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ge = 10 << 28, // N == V Greater or equal.
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lt = 11 << 28, // N != V Less than.
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gt = 12 << 28, // Z clear, N == V Greater than.
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le = 13 << 28, // Z set or N != V Less then or equal
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al = 14 << 28, // Always.
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constexpr Condition eq = 0 << 28; // Z set Equal.
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constexpr Condition ne = 1 << 28; // Z clear Not equal.
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constexpr Condition cs = 2 << 28; // C set Unsigned higher or same.
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constexpr Condition cc = 3 << 28; // C clear Unsigned lower.
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constexpr Condition mi = 4 << 28; // N set Negative.
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constexpr Condition pl = 5 << 28; // N clear Positive or zero.
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constexpr Condition vs = 6 << 28; // V set Overflow.
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constexpr Condition vc = 7 << 28; // V clear No overflow.
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constexpr Condition hi = 8 << 28; // C set, Z clear Unsigned higher.
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constexpr Condition ls = 9 << 28; // C clear or Z set Unsigned lower or same.
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constexpr Condition ge = 10 << 28; // N == V Greater or equal.
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constexpr Condition lt = 11 << 28; // N != V Less than.
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constexpr Condition gt = 12 << 28; // Z clear, N == V Greater than.
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constexpr Condition le = 13 << 28; // Z set or N != V Less then or equal
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constexpr Condition al = 14 << 28; // Always.
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kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
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kNumberOfConditions = 16,
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// Special condition (refer to section A3.2.1).
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constexpr Condition kSpecialCondition = 15 << 28;
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constexpr Condition kNumberOfConditions = 16;
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// Aliases.
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hs = cs, // C set Unsigned higher or same.
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lo = cc // C clear Unsigned lower.
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};
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// Aliases.
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constexpr Condition hs = cs; // C set Unsigned higher or same.
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constexpr Condition lo = cc; // C clear Unsigned lower.
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inline Condition NegateCondition(Condition cond) {
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DCHECK(cond != al);
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@ -116,196 +120,200 @@ using Instr = int32_t;
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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AND = 0 << 21, // Logical AND.
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EOR = 1 << 21, // Logical Exclusive OR.
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SUB = 2 << 21, // Subtract.
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RSB = 3 << 21, // Reverse Subtract.
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ADD = 4 << 21, // Add.
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ADC = 5 << 21, // Add with Carry.
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SBC = 6 << 21, // Subtract with Carry.
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RSC = 7 << 21, // Reverse Subtract with Carry.
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TST = 8 << 21, // Test.
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TEQ = 9 << 21, // Test Equivalence.
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CMP = 10 << 21, // Compare.
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CMN = 11 << 21, // Compare Negated.
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ORR = 12 << 21, // Logical (inclusive) OR.
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MOV = 13 << 21, // Move.
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BIC = 14 << 21, // Bit Clear.
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MVN = 15 << 21 // Move Not.
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};
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using Opcode = int;
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constexpr Opcode AND = 0 << 21; // Logical AND.
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constexpr Opcode EOR = 1 << 21; // Logical Exclusive OR.
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constexpr Opcode SUB = 2 << 21; // Subtract.
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constexpr Opcode RSB = 3 << 21; // Reverse Subtract.
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constexpr Opcode ADD = 4 << 21; // Add.
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constexpr Opcode ADC = 5 << 21; // Add with Carry.
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constexpr Opcode SBC = 6 << 21; // Subtract with Carry.
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constexpr Opcode RSC = 7 << 21; // Reverse Subtract with Carry.
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constexpr Opcode TST = 8 << 21; // Test.
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constexpr Opcode TEQ = 9 << 21; // Test Equivalence.
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constexpr Opcode CMP = 10 << 21; // Compare.
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constexpr Opcode CMN = 11 << 21; // Compare Negated.
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constexpr Opcode ORR = 12 << 21; // Logical (inclusive) OR.
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constexpr Opcode MOV = 13 << 21; // Move.
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constexpr Opcode BIC = 14 << 21; // Bit Clear.
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constexpr Opcode MVN = 15 << 21; // Move Not.
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// The bits for bit 7-4 for some type 0 miscellaneous instructions.
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enum MiscInstructionsBits74 {
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// With bits 22-21 01.
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BX = 1 << 4,
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BXJ = 2 << 4,
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BLX = 3 << 4,
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BKPT = 7 << 4,
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using MiscInstructionsBits74 = int;
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// With bits 22-21 01.
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constexpr MiscInstructionsBits74 BX = 1 << 4;
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constexpr MiscInstructionsBits74 BXJ = 2 << 4;
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constexpr MiscInstructionsBits74 BLX = 3 << 4;
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constexpr MiscInstructionsBits74 BKPT = 7 << 4;
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// With bits 22-21 11.
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CLZ = 1 << 4
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};
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// With bits 22-21 11.
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constexpr MiscInstructionsBits74 CLZ = 1 << 4;
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// Instruction encoding bits and masks.
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enum {
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H = 1 << 5, // Halfword (or byte).
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S6 = 1 << 6, // Signed (or unsigned).
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L = 1 << 20, // Load (or store).
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S = 1 << 20, // Set condition code (or leave unchanged).
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W = 1 << 21, // Writeback base register (or leave unchanged).
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A = 1 << 21, // Accumulate in multiply instruction (or not).
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B = 1 << 22, // Unsigned byte (or word).
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N = 1 << 22, // Long (or short).
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U = 1 << 23, // Positive (or negative) offset/index.
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P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
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I = 1 << 25, // Immediate shifter operand (or not).
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B0 = 1 << 0,
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B4 = 1 << 4,
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B5 = 1 << 5,
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B6 = 1 << 6,
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B7 = 1 << 7,
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B8 = 1 << 8,
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B9 = 1 << 9,
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B10 = 1 << 10,
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B12 = 1 << 12,
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B16 = 1 << 16,
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B17 = 1 << 17,
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B18 = 1 << 18,
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B19 = 1 << 19,
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B20 = 1 << 20,
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B21 = 1 << 21,
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B22 = 1 << 22,
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B23 = 1 << 23,
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B24 = 1 << 24,
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B25 = 1 << 25,
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B26 = 1 << 26,
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B27 = 1 << 27,
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B28 = 1 << 28,
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constexpr int H = 1 << 5; // Halfword (or byte).
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constexpr int S6 = 1 << 6; // Signed (or unsigned).
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constexpr int L = 1 << 20; // Load (or store).
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constexpr int S = 1 << 20; // Set condition code (or leave unchanged).
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constexpr int W = 1 << 21; // Writeback base register (or leave unchanged).
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constexpr int A = 1 << 21; // Accumulate in multiply instruction (or not).
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constexpr int B = 1 << 22; // Unsigned byte (or word).
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constexpr int N = 1 << 22; // Long (or short).
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constexpr int U = 1 << 23; // Positive (or negative) offset/index.
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constexpr int P =
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1 << 24; // Offset/pre-indexed addressing (or post-indexed addressing).
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constexpr int I = 1 << 25; // Immediate shifter operand (or not).
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constexpr int B0 = 1 << 0;
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constexpr int B4 = 1 << 4;
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constexpr int B5 = 1 << 5;
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constexpr int B6 = 1 << 6;
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constexpr int B7 = 1 << 7;
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constexpr int B8 = 1 << 8;
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constexpr int B9 = 1 << 9;
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constexpr int B10 = 1 << 10;
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constexpr int B12 = 1 << 12;
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constexpr int B16 = 1 << 16;
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constexpr int B17 = 1 << 17;
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constexpr int B18 = 1 << 18;
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constexpr int B19 = 1 << 19;
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constexpr int B20 = 1 << 20;
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constexpr int B21 = 1 << 21;
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constexpr int B22 = 1 << 22;
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constexpr int B23 = 1 << 23;
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constexpr int B24 = 1 << 24;
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constexpr int B25 = 1 << 25;
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constexpr int B26 = 1 << 26;
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constexpr int B27 = 1 << 27;
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constexpr int B28 = 1 << 28;
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// Instruction bit masks.
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kCondMask = 15 << 28,
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kALUMask = 0x6f << 21,
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kRdMask = 15 << 12, // In str instruction.
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kCoprocessorMask = 15 << 8,
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kOpCodeMask = 15 << 21, // In data-processing instructions.
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kImm24Mask = (1 << 24) - 1,
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kImm16Mask = (1 << 16) - 1,
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kImm8Mask = (1 << 8) - 1,
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kOff12Mask = (1 << 12) - 1,
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kOff8Mask = (1 << 8) - 1
|
||||
};
|
||||
// Instruction bit masks.
|
||||
constexpr int kCondMask = 15 << 28;
|
||||
constexpr int kALUMask = 0x6f << 21;
|
||||
constexpr int kRdMask = 15 << 12; // In str instruction.
|
||||
constexpr int kCoprocessorMask = 15 << 8;
|
||||
constexpr int kOpCodeMask = 15 << 21; // In data-processing instructions.
|
||||
constexpr int kImm24Mask = (1 << 24) - 1;
|
||||
constexpr int kImm16Mask = (1 << 16) - 1;
|
||||
constexpr int kImm8Mask = (1 << 8) - 1;
|
||||
constexpr int kOff12Mask = (1 << 12) - 1;
|
||||
constexpr int kOff8Mask = (1 << 8) - 1;
|
||||
|
||||
enum BarrierOption {
|
||||
OSHLD = 0x1,
|
||||
OSHST = 0x2,
|
||||
OSH = 0x3,
|
||||
NSHLD = 0x5,
|
||||
NSHST = 0x6,
|
||||
NSH = 0x7,
|
||||
ISHLD = 0x9,
|
||||
ISHST = 0xa,
|
||||
ISH = 0xb,
|
||||
LD = 0xd,
|
||||
ST = 0xe,
|
||||
SY = 0xf,
|
||||
};
|
||||
using BarrierOption = int;
|
||||
constexpr BarrierOption OSHLD = 0x1;
|
||||
constexpr BarrierOption OSHST = 0x2;
|
||||
constexpr BarrierOption OSH = 0x3;
|
||||
constexpr BarrierOption NSHLD = 0x5;
|
||||
constexpr BarrierOption NSHST = 0x6;
|
||||
constexpr BarrierOption NSH = 0x7;
|
||||
constexpr BarrierOption ISHLD = 0x9;
|
||||
constexpr BarrierOption ISHST = 0xa;
|
||||
constexpr BarrierOption ISH = 0xb;
|
||||
constexpr BarrierOption LD = 0xd;
|
||||
constexpr BarrierOption ST = 0xe;
|
||||
constexpr BarrierOption SY = 0xf;
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Addressing modes and instruction variants.
|
||||
|
||||
// Condition code updating mode.
|
||||
enum SBit {
|
||||
SetCC = 1 << 20, // Set condition code.
|
||||
LeaveCC = 0 << 20 // Leave condition code unchanged.
|
||||
};
|
||||
using SBit = int;
|
||||
constexpr SBit SetCC = 1 << 20; // Set condition code.
|
||||
constexpr SBit LeaveCC = 0 << 20; // Leave condition code unchanged.
|
||||
|
||||
// Status register selection.
|
||||
enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 };
|
||||
using SRegister = int;
|
||||
constexpr SRegister CPSR = 0 << 22;
|
||||
constexpr SRegister SPSR = 1 << 22;
|
||||
|
||||
// Shifter types for Data-processing operands as defined in section A5.1.2.
|
||||
enum ShiftOp {
|
||||
LSL = 0 << 5, // Logical shift left.
|
||||
LSR = 1 << 5, // Logical shift right.
|
||||
ASR = 2 << 5, // Arithmetic shift right.
|
||||
ROR = 3 << 5, // Rotate right.
|
||||
using ShiftOp = int;
|
||||
constexpr ShiftOp LSL = 0 << 5; // Logical shift left.
|
||||
constexpr ShiftOp LSR = 1 << 5; // Logical shift right.
|
||||
constexpr ShiftOp ASR = 2 << 5; // Arithmetic shift right.
|
||||
constexpr ShiftOp ROR = 3 << 5; // Rotate right.
|
||||
|
||||
// RRX is encoded as ROR with shift_imm == 0.
|
||||
// Use a special code to make the distinction. The RRX ShiftOp is only used
|
||||
// as an argument, and will never actually be encoded. The Assembler will
|
||||
// detect it and emit the correct ROR shift operand with shift_imm == 0.
|
||||
RRX = -1,
|
||||
kNumberOfShifts = 4
|
||||
};
|
||||
// RRX is encoded as ROR with shift_imm == 0.
|
||||
// Use a special code to make the distinction. The RRX ShiftOp is only used
|
||||
// as an argument, and will never actually be encoded. The Assembler will
|
||||
// detect it and emit the correct ROR shift operand with shift_imm == 0.
|
||||
constexpr ShiftOp RRX = -1;
|
||||
constexpr ShiftOp kNumberOfShifts = 4;
|
||||
|
||||
// Status register fields.
|
||||
enum SRegisterField {
|
||||
CPSR_c = CPSR | 1 << 16,
|
||||
CPSR_x = CPSR | 1 << 17,
|
||||
CPSR_s = CPSR | 1 << 18,
|
||||
CPSR_f = CPSR | 1 << 19,
|
||||
SPSR_c = SPSR | 1 << 16,
|
||||
SPSR_x = SPSR | 1 << 17,
|
||||
SPSR_s = SPSR | 1 << 18,
|
||||
SPSR_f = SPSR | 1 << 19
|
||||
};
|
||||
using SRegisterField = int;
|
||||
constexpr SRegisterField CPSR_c = CPSR | 1 << 16;
|
||||
constexpr SRegisterField CPSR_x = CPSR | 1 << 17;
|
||||
constexpr SRegisterField CPSR_s = CPSR | 1 << 18;
|
||||
constexpr SRegisterField CPSR_f = CPSR | 1 << 19;
|
||||
constexpr SRegisterField SPSR_c = SPSR | 1 << 16;
|
||||
constexpr SRegisterField SPSR_x = SPSR | 1 << 17;
|
||||
constexpr SRegisterField SPSR_s = SPSR | 1 << 18;
|
||||
constexpr SRegisterField SPSR_f = SPSR | 1 << 19;
|
||||
|
||||
// Status register field mask (or'ed SRegisterField enum values).
|
||||
using SRegisterFieldMask = uint32_t;
|
||||
|
||||
// Memory operand addressing mode.
|
||||
enum AddrMode {
|
||||
// Bit encoding P U W.
|
||||
Offset = (8 | 4 | 0) << 21, // Offset (without writeback to base).
|
||||
PreIndex = (8 | 4 | 1) << 21, // Pre-indexed addressing with writeback.
|
||||
PostIndex = (0 | 4 | 0) << 21, // Post-indexed addressing with writeback.
|
||||
NegOffset =
|
||||
(8 | 0 | 0) << 21, // Negative offset (without writeback to base).
|
||||
NegPreIndex = (8 | 0 | 1) << 21, // Negative pre-indexed with writeback.
|
||||
NegPostIndex = (0 | 0 | 0) << 21 // Negative post-indexed with writeback.
|
||||
};
|
||||
using AddrMode = int;
|
||||
// Bit encoding P U W.
|
||||
constexpr AddrMode Offset = (8 | 4 | 0)
|
||||
<< 21; // Offset (without writeback to base).
|
||||
constexpr AddrMode PreIndex = (8 | 4 | 1)
|
||||
<< 21; // Pre-indexed addressing with writeback.
|
||||
constexpr AddrMode PostIndex =
|
||||
(0 | 4 | 0) << 21; // Post-indexed addressing with writeback.
|
||||
constexpr AddrMode NegOffset =
|
||||
(8 | 0 | 0) << 21; // Negative offset (without writeback to base).
|
||||
constexpr AddrMode NegPreIndex = (8 | 0 | 1)
|
||||
<< 21; // Negative pre-indexed with writeback.
|
||||
constexpr AddrMode NegPostIndex =
|
||||
(0 | 0 | 0) << 21; // Negative post-indexed with writeback.
|
||||
|
||||
// Load/store multiple addressing mode.
|
||||
enum BlockAddrMode {
|
||||
// Bit encoding P U W .
|
||||
da = (0 | 0 | 0) << 21, // Decrement after.
|
||||
ia = (0 | 4 | 0) << 21, // Increment after.
|
||||
db = (8 | 0 | 0) << 21, // Decrement before.
|
||||
ib = (8 | 4 | 0) << 21, // Increment before.
|
||||
da_w = (0 | 0 | 1) << 21, // Decrement after with writeback to base.
|
||||
ia_w = (0 | 4 | 1) << 21, // Increment after with writeback to base.
|
||||
db_w = (8 | 0 | 1) << 21, // Decrement before with writeback to base.
|
||||
ib_w = (8 | 4 | 1) << 21, // Increment before with writeback to base.
|
||||
using BlockAddrMode = int;
|
||||
// Bit encoding P U W .
|
||||
constexpr BlockAddrMode da = (0 | 0 | 0) << 21; // Decrement after.
|
||||
constexpr BlockAddrMode ia = (0 | 4 | 0) << 21; // Increment after.
|
||||
constexpr BlockAddrMode db = (8 | 0 | 0) << 21; // Decrement before.
|
||||
constexpr BlockAddrMode ib = (8 | 4 | 0) << 21; // Increment before.
|
||||
constexpr BlockAddrMode da_w =
|
||||
(0 | 0 | 1) << 21; // Decrement after with writeback to base.
|
||||
constexpr BlockAddrMode ia_w =
|
||||
(0 | 4 | 1) << 21; // Increment after with writeback to base.
|
||||
constexpr BlockAddrMode db_w =
|
||||
(8 | 0 | 1) << 21; // Decrement before with writeback to base.
|
||||
constexpr BlockAddrMode ib_w =
|
||||
(8 | 4 | 1) << 21; // Increment before with writeback to base.
|
||||
|
||||
// Alias modes for comparison when writeback does not matter.
|
||||
da_x = (0 | 0 | 0) << 21, // Decrement after.
|
||||
ia_x = (0 | 4 | 0) << 21, // Increment after.
|
||||
db_x = (8 | 0 | 0) << 21, // Decrement before.
|
||||
ib_x = (8 | 4 | 0) << 21, // Increment before.
|
||||
// Alias modes for comparison when writeback does not matter.
|
||||
constexpr BlockAddrMode da_x = (0 | 0 | 0) << 21; // Decrement after.
|
||||
constexpr BlockAddrMode ia_x = (0 | 4 | 0) << 21; // Increment after.
|
||||
constexpr BlockAddrMode db_x = (8 | 0 | 0) << 21; // Decrement before.
|
||||
constexpr BlockAddrMode ib_x = (8 | 4 | 0) << 21; // Increment before.
|
||||
|
||||
kBlockAddrModeMask = (8 | 4 | 1) << 21
|
||||
};
|
||||
constexpr BlockAddrMode kBlockAddrModeMask = (8 | 4 | 1) << 21;
|
||||
|
||||
// Coprocessor load/store operand size.
|
||||
enum LFlag {
|
||||
Long = 1 << 22, // Long load/store coprocessor.
|
||||
Short = 0 << 22 // Short load/store coprocessor.
|
||||
};
|
||||
using LFlag = int;
|
||||
constexpr LFlag Long = 1 << 22; // Long load/store coprocessor.
|
||||
constexpr LFlag Short = 0 << 22; // Short load/store coprocessor.
|
||||
|
||||
// Neon sizes.
|
||||
enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 };
|
||||
using NeonSize = int;
|
||||
constexpr NeonSize Neon8 = 0x0;
|
||||
constexpr NeonSize Neon16 = 0x1;
|
||||
constexpr NeonSize Neon32 = 0x2;
|
||||
constexpr NeonSize Neon64 = 0x3;
|
||||
|
||||
// NEON data type, top bit set for unsigned data types.
|
||||
enum NeonDataType {
|
||||
NeonS8 = 0,
|
||||
NeonS16 = 1,
|
||||
NeonS32 = 2,
|
||||
NeonS64 = 3,
|
||||
NeonU8 = 4,
|
||||
NeonU16 = 5,
|
||||
NeonU32 = 6,
|
||||
NeonU64 = 7
|
||||
};
|
||||
using NeonDataType = int;
|
||||
constexpr NeonDataType NeonS8 = 0;
|
||||
constexpr NeonDataType NeonS16 = 1;
|
||||
constexpr NeonDataType NeonS32 = 2;
|
||||
constexpr NeonDataType NeonS64 = 3;
|
||||
constexpr NeonDataType NeonU8 = 4;
|
||||
constexpr NeonDataType NeonU16 = 5;
|
||||
constexpr NeonDataType NeonU32 = 6;
|
||||
constexpr NeonDataType NeonU64 = 7;
|
||||
|
||||
inline int NeonU(NeonDataType dt) { return static_cast<int>(dt) >> 2; }
|
||||
inline int NeonSz(NeonDataType dt) { return static_cast<int>(dt) & 0x3; }
|
||||
@ -320,7 +328,11 @@ inline NeonSize NeonDataTypeToSize(NeonDataType dt) {
|
||||
return static_cast<NeonSize>(NeonSz(dt));
|
||||
}
|
||||
|
||||
enum NeonListType { nlt_1 = 0x7, nlt_2 = 0xA, nlt_3 = 0x6, nlt_4 = 0x2 };
|
||||
using NeonListType = int;
|
||||
constexpr NeonListType nlt_1 = 0x7;
|
||||
constexpr NeonListType nlt_2 = 0xA;
|
||||
constexpr NeonListType nlt_3 = 0x6;
|
||||
constexpr NeonListType nlt_4 = 0x2;
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Supervisor Call (svc) specific support.
|
||||
@ -329,56 +341,55 @@ enum NeonListType { nlt_1 = 0x7, nlt_2 = 0xA, nlt_3 = 0x6, nlt_4 = 0x2 };
|
||||
// simulator.
|
||||
// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
|
||||
// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
|
||||
enum SoftwareInterruptCodes {
|
||||
// transition to C code
|
||||
kCallRtRedirected = 0x10,
|
||||
// break point
|
||||
kBreakpoint = 0x20,
|
||||
// stop
|
||||
kStopCode = 1 << 23
|
||||
};
|
||||
const uint32_t kStopCodeMask = kStopCode - 1;
|
||||
const uint32_t kMaxStopCode = kStopCode - 1;
|
||||
const int32_t kDefaultStopCode = -1;
|
||||
using SoftwareInterruptCodes = int;
|
||||
// transition to C code
|
||||
constexpr SoftwareInterruptCodes kCallRtRedirected = 0x10;
|
||||
// break point
|
||||
constexpr SoftwareInterruptCodes kBreakpoint = 0x20;
|
||||
// stop
|
||||
constexpr SoftwareInterruptCodes kStopCode = 1 << 23;
|
||||
constexpr uint32_t kStopCodeMask = kStopCode - 1;
|
||||
constexpr uint32_t kMaxStopCode = kStopCode - 1;
|
||||
constexpr int32_t kDefaultStopCode = -1;
|
||||
|
||||
// Type of VFP register. Determines register encoding.
|
||||
enum VFPRegPrecision {
|
||||
kSinglePrecision = 0,
|
||||
kDoublePrecision = 1,
|
||||
kSimd128Precision = 2
|
||||
};
|
||||
using VFPRegPrecision = int;
|
||||
constexpr VFPRegPrecision kSinglePrecision = 0;
|
||||
constexpr VFPRegPrecision kDoublePrecision = 1;
|
||||
constexpr VFPRegPrecision kSimd128Precision = 2;
|
||||
|
||||
// VFP FPSCR constants.
|
||||
enum VFPConversionMode { kFPSCRRounding = 0, kDefaultRoundToZero = 1 };
|
||||
using VFPConversionMode = int;
|
||||
constexpr VFPConversionMode kFPSCRRounding = 0;
|
||||
constexpr VFPConversionMode kDefaultRoundToZero = 1;
|
||||
|
||||
// This mask does not include the "inexact" or "input denormal" cumulative
|
||||
// exceptions flags, because we usually don't want to check for it.
|
||||
const uint32_t kVFPExceptionMask = 0xf;
|
||||
const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
|
||||
const uint32_t kVFPOverflowExceptionBit = 1 << 2;
|
||||
const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
|
||||
const uint32_t kVFPInexactExceptionBit = 1 << 4;
|
||||
const uint32_t kVFPFlushToZeroMask = 1 << 24;
|
||||
const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
|
||||
constexpr uint32_t kVFPExceptionMask = 0xf;
|
||||
constexpr uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
|
||||
constexpr uint32_t kVFPOverflowExceptionBit = 1 << 2;
|
||||
constexpr uint32_t kVFPUnderflowExceptionBit = 1 << 3;
|
||||
constexpr uint32_t kVFPInexactExceptionBit = 1 << 4;
|
||||
constexpr uint32_t kVFPFlushToZeroMask = 1 << 24;
|
||||
constexpr uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
|
||||
|
||||
const uint32_t kVFPNConditionFlagBit = 1 << 31;
|
||||
const uint32_t kVFPZConditionFlagBit = 1 << 30;
|
||||
const uint32_t kVFPCConditionFlagBit = 1 << 29;
|
||||
const uint32_t kVFPVConditionFlagBit = 1 << 28;
|
||||
constexpr uint32_t kVFPNConditionFlagBit = 1 << 31;
|
||||
constexpr uint32_t kVFPZConditionFlagBit = 1 << 30;
|
||||
constexpr uint32_t kVFPCConditionFlagBit = 1 << 29;
|
||||
constexpr uint32_t kVFPVConditionFlagBit = 1 << 28;
|
||||
|
||||
// VFP rounding modes. See ARM DDI 0406B Page A2-29.
|
||||
enum VFPRoundingMode {
|
||||
RN = 0 << 22, // Round to Nearest.
|
||||
RP = 1 << 22, // Round towards Plus Infinity.
|
||||
RM = 2 << 22, // Round towards Minus Infinity.
|
||||
RZ = 3 << 22, // Round towards zero.
|
||||
using VFPRoundingMode = int;
|
||||
constexpr VFPRoundingMode RN = 0 << 22; // Round to Nearest.
|
||||
constexpr VFPRoundingMode RP = 1 << 22; // Round towards Plus Infinity.
|
||||
constexpr VFPRoundingMode RM = 2 << 22; // Round towards Minus Infinity.
|
||||
constexpr VFPRoundingMode RZ = 3 << 22; // Round towards zero.
|
||||
|
||||
// Aliases.
|
||||
kRoundToNearest = RN,
|
||||
kRoundToPlusInf = RP,
|
||||
kRoundToMinusInf = RM,
|
||||
kRoundToZero = RZ
|
||||
};
|
||||
// Aliases.
|
||||
constexpr VFPRoundingMode kRoundToNearest = RN;
|
||||
constexpr VFPRoundingMode kRoundToPlusInf = RP;
|
||||
constexpr VFPRoundingMode kRoundToMinusInf = RM;
|
||||
constexpr VFPRoundingMode kRoundToZero = RZ;
|
||||
|
||||
const uint32_t kVFPRoundingModeMask = 3 << 22;
|
||||
|
||||
|
||||
@ -392,11 +392,6 @@ void TurboAssembler::Drop(Register count, Condition cond) {
|
||||
add(sp, sp, Operand(count, LSL, kPointerSizeLog2), LeaveCC, cond);
|
||||
}
|
||||
|
||||
void TurboAssembler::Ret(int drop, Condition cond) {
|
||||
Drop(drop, cond);
|
||||
Ret(cond);
|
||||
}
|
||||
|
||||
void MacroAssembler::TestCodeTIsMarkedForDeoptimization(Register codet,
|
||||
Register scratch) {
|
||||
ldr(scratch, FieldMemOperand(codet, Code::kCodeDataContainerOffset));
|
||||
|
||||
@ -332,7 +332,6 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
|
||||
void Drop(Register count, Condition cond = al);
|
||||
|
||||
void Ret(Condition cond = al);
|
||||
void Ret(int drop, Condition cond = al);
|
||||
|
||||
// Compare single values and move the result to the normal condition flags.
|
||||
void VFPCompareAndSetFlags(const SwVfpRegister src1, const SwVfpRegister src2,
|
||||
|
||||
@ -390,7 +390,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
|
||||
__ dmb(ISH); \
|
||||
__ bind(&binop); \
|
||||
__ ldrexd(r2, r3, i.TempRegister(0)); \
|
||||
__ instr1(i.TempRegister(1), r2, i.InputRegister(0), SBit::SetCC); \
|
||||
__ instr1(i.TempRegister(1), r2, i.InputRegister(0), SetCC); \
|
||||
__ instr2(i.TempRegister(2), r3, Operand(i.InputRegister(1))); \
|
||||
DCHECK_EQ(LeaveCC, i.OutputSBit()); \
|
||||
__ strexd(i.TempRegister(3), i.TempRegister(1), i.TempRegister(2), \
|
||||
@ -1224,7 +1224,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
||||
// i.InputRegister(2) ... right low word.
|
||||
// i.InputRegister(3) ... right high word.
|
||||
__ add(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2),
|
||||
SBit::SetCC);
|
||||
SetCC);
|
||||
__ adc(i.OutputRegister(1), i.InputRegister(1),
|
||||
Operand(i.InputRegister(3)));
|
||||
DCHECK_EQ(LeaveCC, i.OutputSBit());
|
||||
@ -1235,7 +1235,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
||||
// i.InputRegister(2) ... right low word.
|
||||
// i.InputRegister(3) ... right high word.
|
||||
__ sub(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2),
|
||||
SBit::SetCC);
|
||||
SetCC);
|
||||
__ sbc(i.OutputRegister(1), i.InputRegister(1),
|
||||
Operand(i.InputRegister(3)));
|
||||
DCHECK_EQ(LeaveCC, i.OutputSBit());
|
||||
@ -1520,7 +1520,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
||||
// Avoid INT32_MAX as an overflow indicator and use INT32_MIN instead,
|
||||
// because INT32_MIN allows easier out-of-bounds detection.
|
||||
__ cmn(i.OutputRegister(), Operand(1));
|
||||
__ mov(i.OutputRegister(), Operand(INT32_MIN), SBit::LeaveCC, vs);
|
||||
__ mov(i.OutputRegister(), Operand(INT32_MIN), LeaveCC, vs);
|
||||
}
|
||||
DCHECK_EQ(LeaveCC, i.OutputSBit());
|
||||
break;
|
||||
|
||||
@ -385,6 +385,9 @@ constexpr int MaskFromNeonDataType(NeonDataType dt) {
|
||||
case NeonS64:
|
||||
case NeonU64:
|
||||
return 63;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -58,7 +58,7 @@ TEST_F(TurboAssemblerTest, TestCheck) {
|
||||
// Fail if the first parameter is 17.
|
||||
__ Move32BitImmediate(r1, Operand(17));
|
||||
__ cmp(r0, r1); // 1st parameter is in {r0}.
|
||||
__ Check(Condition::ne, AbortReason::kNoReason);
|
||||
__ Check(ne, AbortReason::kNoReason);
|
||||
__ Ret();
|
||||
|
||||
CodeDesc desc;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user