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[wasm] Add simd replaceLane ops to wasm interpreter

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Also enables tests for globals and mixed type use

R=gdeepti@chromium.org,bbudge@chromium.org,clemensh@chromium.org,titzer@chromium.org
BUG=v8:6020

Change-Id: I828f1628a1c27d9f07ba3a830600f81c5a404b2d
Reviewed-on: https://chromium-review.googlesource.com/1080340
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Commit-Queue: Aseem Garg <aseemgarg@chromium.org>
Cr-Commit-Position: refs/heads/master@{#53477}
This commit is contained in:
Aseem Garg 2018-05-31 14:38:23 -07:00 committed by Commit Bot
parent 91df12aa36
commit dc6819ec56
4 changed files with 56 additions and 32 deletions
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4
src/wasm/function-body-decoder-impl.h
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@ -1143,8 +1143,10 @@ class WasmDecoder : public Decoder {
case kExprI32AtomicStore16U:
case kExprS128StoreMem:
return {2, 0};
FOREACH_SIMD_1_OPERAND_OPCODE(DECLARE_OPCODE_CASE)
FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(DECLARE_OPCODE_CASE)
return {1, 1};
FOREACH_SIMD_1_OPERAND_2_PARAM_OPCODE(DECLARE_OPCODE_CASE)
return {2, 1};
default: {
sig = WasmOpcodes::Signature(opcode);
if (sig) {

16
src/wasm/wasm-interpreter.cc
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@ -1827,6 +1827,22 @@ class ThreadImpl {
I8x16LeU, i8x16, int16, int16, 16,
*reinterpret_cast<uint8_t*>(&a) <= *reinterpret_cast<uint8_t*>(&b))
#undef CMPOP_CASE
#define REPLACE_LANE_CASE(format, name, stype, ctype) \
case kExpr##format##ReplaceLane: { \
SimdLaneImmediate<Decoder::kNoValidate> imm(decoder, code->at(pc)); \
++len; \
WasmValue new_val = Pop(); \
WasmValue simd_val = Pop(); \
stype s = simd_val.to_s128().to_##name(); \
s.val[imm.lane] = new_val.to<ctype>(); \
Push(WasmValue(Simd128(s))); \
return true; \
}
REPLACE_LANE_CASE(F32x4, f32x4, float4, float)
REPLACE_LANE_CASE(I32x4, i32x4, int4, int32_t)
REPLACE_LANE_CASE(I16x8, i16x8, int8, int32_t)
REPLACE_LANE_CASE(I8x16, i8x16, int16, int32_t)
#undef REPLACE_LANE_CASE
default:
return false;
}

40
src/wasm/wasm-opcodes.h
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@ -376,25 +376,31 @@ using WasmName = Vector<const char>;
V(S1x16AnyTrue, 0xfd90, i_s) \
V(S1x16AllTrue, 0xfd91, i_s)
#define FOREACH_SIMD_1_OPERAND_OPCODE(V) \
V(F32x4ExtractLane, 0xfd01, _) \
V(F32x4ReplaceLane, 0xfd02, _) \
V(I32x4ExtractLane, 0xfd1c, _) \
V(I32x4ReplaceLane, 0xfd1d, _) \
V(I32x4Shl, 0xfd24, _) \
V(I32x4ShrS, 0xfd25, _) \
V(I32x4ShrU, 0xfd32, _) \
V(I16x8ExtractLane, 0xfd39, _) \
V(I16x8ReplaceLane, 0xfd3a, _) \
V(I16x8Shl, 0xfd43, _) \
V(I16x8ShrS, 0xfd44, _) \
V(I16x8ShrU, 0xfd52, _) \
V(I8x16ExtractLane, 0xfd58, _) \
V(I8x16ReplaceLane, 0xfd59, _) \
V(I8x16Shl, 0xfd62, _) \
V(I8x16ShrS, 0xfd63, _) \
#define FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \
V(F32x4ExtractLane, 0xfd01, _) \
V(I32x4ExtractLane, 0xfd1c, _) \
V(I32x4Shl, 0xfd24, _) \
V(I32x4ShrS, 0xfd25, _) \
V(I32x4ShrU, 0xfd32, _) \
V(I16x8ExtractLane, 0xfd39, _) \
V(I16x8Shl, 0xfd43, _) \
V(I16x8ShrS, 0xfd44, _) \
V(I16x8ShrU, 0xfd52, _) \
V(I8x16ExtractLane, 0xfd58, _) \
V(I8x16Shl, 0xfd62, _) \
V(I8x16ShrS, 0xfd63, _) \
V(I8x16ShrU, 0xfd71, _)
#define FOREACH_SIMD_1_OPERAND_2_PARAM_OPCODE(V) \
V(F32x4ReplaceLane, 0xfd02, _) \
V(I32x4ReplaceLane, 0xfd1d, _) \
V(I16x8ReplaceLane, 0xfd3a, _) \
V(I8x16ReplaceLane, 0xfd59, _)
#define FOREACH_SIMD_1_OPERAND_OPCODE(V) \
FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \
FOREACH_SIMD_1_OPERAND_2_PARAM_OPCODE(V)
#define FOREACH_SIMD_MASK_OPERAND_OPCODE(V) V(S8x16Shuffle, 0xfd6b, s_ss)
#define FOREACH_SIMD_MEM_OPCODE(V) \

28
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -436,7 +436,7 @@ WASM_SIMD_TEST(F32x4Splat) {
}
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(F32x4ReplaceLane) {
WASM_SIMD_TEST(F32x4ReplaceLane) {
WasmRunner<int32_t, float, float> r(execution_mode, lower_simd);
byte old_val = 0;
byte new_val = 1;
@ -643,7 +643,7 @@ WASM_SIMD_TEST(I32x4Splat) {
FOR_INT32_INPUTS(i) { CHECK_EQ(1, r.Call(*i)); }
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(I32x4ReplaceLane) {
WASM_SIMD_TEST(I32x4ReplaceLane) {
WasmRunner<int32_t, int32_t, int32_t> r(execution_mode, lower_simd);
byte old_val = 0;
byte new_val = 1;
@ -680,7 +680,7 @@ WASM_SIMD_TEST(I16x8Splat) {
FOR_INT16_INPUTS(i) { CHECK_EQ(1, r.Call(*i)); }
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(I16x8ReplaceLane) {
WASM_SIMD_TEST(I16x8ReplaceLane) {
WasmRunner<int32_t, int32_t, int32_t> r(execution_mode, lower_simd);
byte old_val = 0;
byte new_val = 1;
@ -740,7 +740,7 @@ WASM_SIMD_TEST(I8x16Splat) {
FOR_INT8_INPUTS(i) { CHECK_EQ(1, r.Call(*i)); }
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(I8x16ReplaceLane) {
WASM_SIMD_TEST(I8x16ReplaceLane) {
WasmRunner<int32_t, int32_t, int32_t> r(execution_mode, lower_simd);
byte old_val = 0;
byte new_val = 1;
@ -2044,7 +2044,7 @@ WASM_SIMD_BOOL_REDUCTION_TEST(32x4, 4)
WASM_SIMD_BOOL_REDUCTION_TEST(16x8, 8)
WASM_SIMD_BOOL_REDUCTION_TEST(8x16, 16)
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4ExtractWithF32x4) {
WASM_SIMD_TEST(SimdI32x4ExtractWithF32x4) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
BUILD(r, WASM_IF_ELSE_I(
WASM_I32_EQ(WASM_SIMD_I32x4_EXTRACT_LANE(
@ -2056,7 +2056,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4ExtractWithF32x4) {
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdF32x4ExtractWithI32x4) {
WASM_SIMD_TEST(SimdF32x4ExtractWithI32x4) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
BUILD(r,
WASM_IF_ELSE_I(WASM_F32_EQ(WASM_SIMD_F32x4_EXTRACT_LANE(
@ -2100,7 +2100,7 @@ WASM_SIMD_TEST(SimdI32x4AddWithF32x4) {
CHECK_EQ(1, r.Call());
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4Local) {
WASM_SIMD_TEST(SimdI32x4Local) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
r.AllocateLocal(kWasmS128);
BUILD(r, WASM_SET_LOCAL(0, WASM_SIMD_I32x4_SPLAT(WASM_I32V(31))),
@ -2109,7 +2109,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4Local) {
CHECK_EQ(31, r.Call());
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4SplatFromExtract) {
WASM_SIMD_TEST(SimdI32x4SplatFromExtract) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
r.AllocateLocal(kWasmI32);
r.AllocateLocal(kWasmS128);
@ -2120,7 +2120,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4SplatFromExtract) {
CHECK_EQ(76, r.Call());
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4For) {
WASM_SIMD_TEST(SimdI32x4For) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
r.AllocateLocal(kWasmI32);
r.AllocateLocal(kWasmS128);
@ -2154,7 +2154,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4For) {
CHECK_EQ(1, r.Call());
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdF32x4For) {
WASM_SIMD_TEST(SimdF32x4For) {
WasmRunner<int32_t> r(execution_mode, lower_simd);
r.AllocateLocal(kWasmI32);
r.AllocateLocal(kWasmS128);
@ -2203,7 +2203,7 @@ const T& GetScalar(T* v, int lane) {
return v[index];
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4GetGlobal) {
WASM_SIMD_TEST(SimdI32x4GetGlobal) {
WasmRunner<int32_t, int32_t> r(execution_mode, lower_simd);
// Pad the globals with a few unused slots to get a non-zero offset.
r.builder().AddGlobal<int32_t>(kWasmI32); // purposefully unused
@ -2231,7 +2231,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4GetGlobal) {
CHECK_EQ(1, r.Call(0));
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4SetGlobal) {
WASM_SIMD_TEST(SimdI32x4SetGlobal) {
WasmRunner<int32_t, int32_t> r(execution_mode, lower_simd);
// Pad the globals with a few unused slots to get a non-zero offset.
r.builder().AddGlobal<int32_t>(kWasmI32); // purposefully unused
@ -2254,7 +2254,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdI32x4SetGlobal) {
CHECK_EQ(GetScalar(global, 3), 56);
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdF32x4GetGlobal) {
WASM_SIMD_TEST(SimdF32x4GetGlobal) {
WasmRunner<int32_t, int32_t> r(execution_mode, lower_simd);
float* global = r.builder().AddGlobal<float>(kWasmS128);
SetVectorByLanes<float>(global, {{0.0, 1.5, 2.25, 3.5}});
@ -2277,7 +2277,7 @@ WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdF32x4GetGlobal) {
CHECK_EQ(1, r.Call(0));
}
WASM_SIMD_COMPILED_AND_LOWERED_TEST(SimdF32x4SetGlobal) {
WASM_SIMD_TEST(SimdF32x4SetGlobal) {
WasmRunner<int32_t, int32_t> r(execution_mode, lower_simd);
float* global = r.builder().AddGlobal<float>(kWasmS128);
BUILD(r, WASM_SET_GLOBAL(0, WASM_SIMD_F32x4_SPLAT(WASM_F32(13.5))),