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Generate more compact XOR on 64-bit architecture when using xor to zero out registers.

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When using xor to zero a 64-bit register, generate 32-bit instruction instead.
(according to Intel 64-bit mode coding guidelines) 

previous code for zeroing RAX:
  xor rax, rax  

==>

new code for zeroing RAX: 
  xor eax, eax

The 32-bit operand form has the same semantics: It also zeroes the upper 
32-bit of rax and its encoding uses 1 byte less.

Review URL: http://codereview.chromium.org/330018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3132 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
fschneider@chromium.org 2009-10-26 14:38:22 +00:00
parent d59f47a2d5
commit dcee14979f
1 changed files with 5 additions and 1 deletions
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6
src/x64/assembler-x64.h
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@ -920,7 +920,11 @@ class Assembler : public Malloced {
void testq(Register dst, Immediate mask);
void xor_(Register dst, Register src) {
arithmetic_op(0x33, dst, src);
if (dst.code() == src.code()) {
arithmetic_op_32(0x33, dst, src);
} else {
arithmetic_op(0x33, dst, src);
}
}
void xorl(Register dst, Register src) {