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[wasm] Int64Lowering of I64Shl on ia32.

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I64Shl is lowered to a new turbofan operator, WasmWord64Shl. The new
operator takes 3 inputs, the low-word input, the high-word input, and
the shift, and produces 2 output, the low-word output and the high-word
output.

At the moment I implemented the lowering only for ia32, but I think the
CL is already big enough. I will add the other platforms in separate
CLs.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/1756863002

Cr-Commit-Position: refs/heads/master@{#34546}
This commit is contained in:
ahaas 2016-03-07 07:17:54 -08:00 committed by Commit bot
parent b455e2b2a0
commit ddc626e1cf
26 changed files with 254 additions and 30 deletions
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1
src/compiler/arm/instruction-selector-arm.cc
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@ -769,6 +769,7 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
VisitShift(this, node, TryMatchASR);
}
void InstructionSelector::VisitWord32PairShl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitWord32Ror(Node* node) {
VisitShift(this, node, TryMatchROR);

8
src/compiler/ia32/code-generator-ia32.cc
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@ -632,6 +632,14 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ sar_cl(i.OutputOperand());
}
break;
case kIA32PairShl:
if (HasImmediateInput(instr, 2)) {
__ PairShl(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));
} else {
// Shift has been loaded into CL by the register allocator.
__ PairShl_cl(i.InputRegister(1), i.InputRegister(0));
}
break;
case kIA32Ror:
if (HasImmediateInput(instr, 1)) {
__ ror(i.OutputOperand(), i.InputInt5(1));

2
src/compiler/ia32/instruction-codes-ia32.h
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@ -29,6 +29,7 @@ namespace compiler {
V(IA32Shl) \
V(IA32Shr) \
V(IA32Sar) \
V(IA32PairShl) \
V(IA32Ror) \
V(IA32Lzcnt) \
V(IA32Tzcnt) \
@ -105,7 +106,6 @@ namespace compiler {
V(IA32Poke) \
V(IA32StackCheck)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes
// are encoded into the InstructionCode of the instruction and tell the

1
src/compiler/ia32/instruction-scheduler-ia32.cc
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@ -31,6 +31,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kIA32Shl:
case kIA32Shr:
case kIA32Sar:
case kIA32PairShl:
case kIA32Ror:
case kIA32Lzcnt:
case kIA32Tzcnt:

20
src/compiler/ia32/instruction-selector-ia32.cc
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@ -585,6 +585,26 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
VisitShift(this, node, kIA32Sar);
}
void InstructionSelector::VisitWord32PairShl(Node* node) {
IA32OperandGenerator g(this);
Node* shift = node->InputAt(2);
InstructionOperand shift_operand;
if (g.CanBeImmediate(shift)) {
shift_operand = g.UseImmediate(shift);
} else {
shift_operand = g.UseFixed(shift, ecx);
}
InstructionOperand inputs[] = {g.UseFixed(node->InputAt(0), eax),
g.UseFixed(node->InputAt(1), edx),
shift_operand};
InstructionOperand outputs[] = {
g.DefineAsFixed(node, eax),
g.DefineAsFixed(NodeProperties::FindProjection(node, 1), edx)};
Emit(kIA32PairShl, 2, outputs, 3, inputs);
}
void InstructionSelector::VisitWord32Ror(Node* node) {
VisitShift(this, node, kIA32Ror);

9
src/compiler/instruction-selector.cc
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@ -1150,6 +1150,10 @@ void InstructionSelector::VisitNode(Node* node) {
}
case IrOpcode::kCheckedStore:
return VisitCheckedStore(node);
case IrOpcode::kWord32PairShl:
MarkAsWord32(NodeProperties::FindProjection(node, 0));
MarkAsWord32(NodeProperties::FindProjection(node, 1));
return VisitWord32PairShl(node);
default:
V8_Fatal(__FILE__, __LINE__, "Unexpected operator #%d:%s @ node #%d",
node->opcode(), node->op()->mnemonic(), node->id());
@ -1373,6 +1377,10 @@ void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
#endif // V8_TARGET_ARCH_32_BIT
// 32 bit targets do not implement the following instructions.
#if V8_TARGET_ARCH_64_BIT
void InstructionSelector::VisitWord32PairShl(Node* node) { UNIMPLEMENTED(); }
#endif // V8_TARGET_ARCH_64_BIT
void InstructionSelector::VisitFinishRegion(Node* node) {
OperandGenerator g(this);
@ -1451,6 +1459,7 @@ void InstructionSelector::VisitProjection(Node* node) {
case IrOpcode::kTryTruncateFloat64ToInt64:
case IrOpcode::kTryTruncateFloat32ToUint64:
case IrOpcode::kTryTruncateFloat64ToUint64:
case IrOpcode::kWord32PairShl:
if (ProjectionIndexOf(node->op()) == 0u) {
Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
} else {

22
src/compiler/int64-lowering.cc
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@ -289,6 +289,28 @@ void Int64Lowering::LowerNode(Node* node) {
break;
}
// kExprI64Shl:
case IrOpcode::kWord64Shl: {
// TODO(turbofan): if the shift count >= 32, then we can set the low word
// of the output to 0 and just calculate the high word.
DCHECK(node->InputCount() == 2);
Node* shift = node->InputAt(1);
if (HasReplacementLow(shift)) {
// We do not have to care about the high word replacement, because
// the shift can only be between 0 and 63 anyways.
node->ReplaceInput(1, GetReplacementLow(shift));
}
Node* value = node->InputAt(0);
node->ReplaceInput(0, GetReplacementLow(value));
node->InsertInput(zone(), 1, GetReplacementHigh(value));
NodeProperties::ChangeOp(node, machine()->Word32PairShl());
// We access the additional return values through projections.
Node* low_node = graph()->NewNode(common()->Projection(0), node);
Node* high_node = graph()->NewNode(common()->Projection(1), node);
ReplaceNode(node, low_node, high_node);
break;
}
// kExprI64ShrU:
// kExprI64ShrS:
// kExprI64Eq:

3
src/compiler/machine-operator.cc
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@ -195,7 +195,8 @@ MachineRepresentation StackSlotRepresentationOf(Operator const* op) {
V(Float64InsertHighWord32, Operator::kNoProperties, 2, 0, 1) \
V(LoadStackPointer, Operator::kNoProperties, 0, 0, 1) \
V(LoadFramePointer, Operator::kNoProperties, 0, 0, 1) \
V(LoadParentFramePointer, Operator::kNoProperties, 0, 0, 1)
V(LoadParentFramePointer, Operator::kNoProperties, 0, 0, 1) \
V(Word32PairShl, Operator::kNoProperties, 3, 0, 2)
#define PURE_OPTIONAL_OP_LIST(V) \
V(Word32Ctz, Operator::kNoProperties, 1, 0, 1) \

2
src/compiler/machine-operator.h
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@ -179,6 +179,8 @@ class MachineOperatorBuilder final : public ZoneObject {
const OptionalOperator Word64Ctz();
const Operator* Word64Equal();
const Operator* Word32PairShl();
const Operator* Int32Add();
const Operator* Int32AddWithOverflow();
const Operator* Int32Sub();

1
src/compiler/mips/instruction-selector-mips.cc
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@ -397,6 +397,7 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
VisitRRO(this, kMipsSar, node);
}
void InstructionSelector::VisitWord32PairShl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitWord32Ror(Node* node) {
VisitRRO(this, kMipsRor, node);

3
src/compiler/opcodes.h
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@ -333,7 +333,8 @@
V(LoadFramePointer) \
V(LoadParentFramePointer) \
V(CheckedLoad) \
V(CheckedStore)
V(CheckedStore) \
V(Word32PairShl)
#define VALUE_OP_LIST(V) \
COMMON_OP_LIST(V) \

3
src/compiler/raw-machine-assembler.h
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@ -324,6 +324,9 @@ class RawMachineAssembler {
Node* Uint64Mod(Node* a, Node* b) {
return AddNode(machine()->Uint64Mod(), a, b);
}
Node* Word32PairShl(Node* low_word, Node* high_word, Node* shift) {
return AddNode(machine()->Word32PairShl(), low_word, high_word, shift);
}
#define INTPTR_BINOP(prefix, name) \
Node* IntPtr##name(Node* a, Node* b) { \

1
src/compiler/typer.cc
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@ -2441,6 +2441,7 @@ Type* Typer::Visitor::TypeCheckedStore(Node* node) {
return nullptr;
}
Type* Typer::Visitor::TypeWord32PairShl(Node* node) { return Type::Internal(); }
// Heap constants.

1
src/compiler/verifier.cc
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@ -951,6 +951,7 @@ void Verifier::Visitor::Check(Node* node) {
case IrOpcode::kFloat64ExtractHighWord32:
case IrOpcode::kFloat64InsertLowWord32:
case IrOpcode::kFloat64InsertHighWord32:
case IrOpcode::kWord32PairShl:
case IrOpcode::kLoadStackPointer:
case IrOpcode::kLoadFramePointer:
case IrOpcode::kLoadParentFramePointer:

12
src/compiler/wasm-compiler.cc
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@ -509,9 +509,12 @@ Node* WasmGraphBuilder::Binop(wasm::WasmOpcode opcode, Node* left,
op = m->Word64Xor();
break;
// kExprI64Shl:
// kExprI64ShrU:
// kExprI64ShrS:
// kExprI64Eq:
case wasm::kExprI64Shl:
op = m->Word64Shl();
break;
// kExprI64ShrU:
// kExprI64ShrS:
// kExprI64Eq:
case wasm::kExprI64Eq:
op = m->Word64Equal();
break;
@ -598,9 +601,6 @@ Node* WasmGraphBuilder::Binop(wasm::WasmOpcode opcode, Node* left,
op = m->Uint64Mod();
return graph()->NewNode(op, left, right,
trap_->ZeroCheck64(kTrapRemByZero, right));
case wasm::kExprI64Shl:
op = m->Word64Shl();
break;
case wasm::kExprI64ShrU:
op = m->Word64Shr();
break;

1
src/compiler/x87/instruction-selector-x87.cc
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@ -546,6 +546,7 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
VisitShift(this, node, kX87Sar);
}
void InstructionSelector::VisitWord32PairShl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitWord32Ror(Node* node) {
VisitShift(this, node, kX87Ror);

12
src/ia32/assembler-ia32.cc
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@ -1075,12 +1075,20 @@ void Assembler::sbb(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::shld(Register dst, Register src, uint8_t shift) {
DCHECK(is_uint5(shift));
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xA4);
emit_operand(src, Operand(dst));
EMIT(shift);
}
void Assembler::shld(Register dst, const Operand& src) {
void Assembler::shld_cl(Register dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xA5);
emit_operand(dst, src);
emit_operand(src, Operand(dst));
}

4
src/ia32/assembler-ia32.h
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@ -738,8 +738,8 @@ class Assembler : public AssemblerBase {
void sbb(Register dst, const Operand& src);
void shld(Register dst, Register src) { shld(dst, Operand(src)); }
void shld(Register dst, const Operand& src);
void shld(Register dst, Register src, uint8_t shift);
void shld_cl(Register dst, Register src);
void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
void shl(const Operand& dst, uint8_t imm8);

49
src/ia32/disasm-ia32.cc
View File

@ -1218,20 +1218,34 @@ static const char* F0Mnem(byte f0byte) {
switch (f0byte) {
case 0x0B:
return "ud2";
case 0x18: return "prefetch";
case 0xA2: return "cpuid";
case 0xBE: return "movsx_b";
case 0xBF: return "movsx_w";
case 0xB6: return "movzx_b";
case 0xB7: return "movzx_w";
case 0xAF: return "imul";
case 0xA5: return "shld";
case 0xAD: return "shrd";
case 0xAC: return "shrd"; // 3-operand version.
case 0xAB: return "bts";
case 0x18:
return "prefetch";
case 0xA2:
return "cpuid";
case 0xBE:
return "movsx_b";
case 0xBF:
return "movsx_w";
case 0xB6:
return "movzx_b";
case 0xB7:
return "movzx_w";
case 0xAF:
return "imul";
case 0xA4:
return "shld";
case 0xA5:
return "shld";
case 0xAD:
return "shrd";
case 0xAC:
return "shrd"; // 3-operand version.
case 0xAB:
return "bts";
case 0xBC:
return "bsf";
case 0xBD: return "bsr";
case 0xBD:
return "bsr";
default: return NULL;
}
}
@ -1470,8 +1484,17 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
data += SetCC(data);
} else if ((f0byte & 0xF0) == 0x40) {
data += CMov(data);
} else if (f0byte == 0xA4) {
data += 2;
AppendToBuffer("%s ", f0mnem);
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
int8_t imm8 = static_cast<int8_t>(data[1]);
data += 2;
AppendToBuffer("%s,%s,%d", NameOfCPURegister(rm),
NameOfCPURegister(regop), static_cast<int>(imm8));
} else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
// shrd, shld, bts
// shrd, shld_cl, bts
data += 2;
AppendToBuffer("%s ", f0mnem);
int mod, regop, rm;

22
src/ia32/macro-assembler-ia32.cc
View File

@ -682,7 +682,6 @@ void MacroAssembler::DebugBreak() {
call(ces.GetCode(), RelocInfo::DEBUGGER_STATEMENT);
}
void MacroAssembler::Cvtsi2sd(XMMRegister dst, const Operand& src) {
xorps(dst, dst);
cvtsi2sd(dst, src);
@ -707,6 +706,27 @@ void MacroAssembler::Cvtui2ss(XMMRegister dst, Register src, Register tmp) {
bind(&jmp_return);
}
void MacroAssembler::PairShl(Register dst, Register src, uint8_t shift) {
if (shift >= 32) {
mov(dst, src);
shl(dst, shift - 32);
xor_(src, src);
} else {
shld(dst, src, shift);
shl(src, shift);
}
}
void MacroAssembler::PairShl_cl(Register dst, Register src) {
shld_cl(dst, src);
shl_cl(src);
Label done;
test(ecx, Immediate(0x20));
j(equal, &done, Label::kNear);
mov(dst, src);
xor_(src, src);
bind(&done);
}
bool MacroAssembler::IsUnsafeImmediate(const Immediate& x) {
static const int kMaxImmediateBits = 17;

3
src/ia32/macro-assembler-ia32.h
View File

@ -370,6 +370,9 @@ class MacroAssembler: public Assembler {
void Cvtui2ss(XMMRegister dst, Register src, Register tmp);
void PairShl(Register dst, Register src, uint8_t imm8);
void PairShl_cl(Register dst, Register src);
// Support for constant splitting.
bool IsUnsafeImmediate(const Immediate& x);
void SafeMove(Register dst, const Immediate& x);

4
test/cctest/test-disasm-ia32.cc
View File

@ -119,7 +119,8 @@ TEST(DisasmIa320) {
__ nop();
__ imul(edx, ecx);
__ shld(edx, ecx);
__ shld(edx, ecx, 10);
__ shld_cl(edx, ecx);
__ shrd(edx, ecx);
__ bts(edx, ecx);
__ bts(Operand(ebx, ecx, times_4, 0), ecx);
@ -214,7 +215,6 @@ TEST(DisasmIa320) {
__ sar(Operand(ebx, ecx, times_4, 10000), 6);
__ sar_cl(Operand(ebx, ecx, times_4, 10000));
__ sbb(edx, Operand(ebx, ecx, times_4, 10000));
__ shld(edx, Operand(ebx, ecx, times_4, 10000));
__ shl(edx, 1);
__ shl(edx, 6);
__ shl_cl(edx);

33
test/cctest/wasm/test-run-wasm-64.cc
View File

@ -51,6 +51,39 @@ TEST(Run_WasmI64Xor) {
}
}
// kExprI64Shl:
#if !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_X87 && !V8_TARGET_ARCH_ARM
TEST(Run_WasmI64Shl) {
{
WasmRunner<int64_t> r(MachineType::Int64(), MachineType::Int64());
BUILD(r, WASM_I64_SHL(WASM_GET_LOCAL(0), WASM_GET_LOCAL(1)));
FOR_UINT64_INPUTS(i) {
for (int64_t j = 1; j < 64; j++) {
CHECK_EQ(*i << j, r.Call(*i, j));
}
}
}
{
WasmRunner<int64_t> r(MachineType::Int64());
BUILD(r, WASM_I64_SHL(WASM_GET_LOCAL(0), WASM_I64V_1(0)));
FOR_UINT64_INPUTS(i) { CHECK_EQ(*i << 0, r.Call(*i)); }
}
{
WasmRunner<int64_t> r(MachineType::Int64());
BUILD(r, WASM_I64_SHL(WASM_GET_LOCAL(0), WASM_I64V_1(32)));
FOR_UINT64_INPUTS(i) { CHECK_EQ(*i << 32, r.Call(*i)); }
}
{
WasmRunner<int64_t> r(MachineType::Int64());
BUILD(r, WASM_I64_SHL(WASM_GET_LOCAL(0), WASM_I64V_1(20)));
FOR_UINT64_INPUTS(i) { CHECK_EQ(*i << 20, r.Call(*i)); }
}
{
WasmRunner<int64_t> r(MachineType::Int64());
BUILD(r, WASM_I64_SHL(WASM_GET_LOCAL(0), WASM_I64V_1(40)));
FOR_UINT64_INPUTS(i) { CHECK_EQ(*i << 40, r.Call(*i)); }
}
}
#endif
// kExprI64ShrU:
// kExprI64ShrS:
// kExprI64Eq:

17
test/unittests/compiler/int64-lowering-unittest.cc
View File

@ -356,6 +356,23 @@ TEST_F(Int64LoweringTest, Int64Xor) {
start(), start()));
}
// kExprI64Shl:
TEST_F(Int64LoweringTest, Int64Shl) {
if (4 != kPointerSize) return;
LowerGraph(graph()->NewNode(machine()->Word64Shl(), Int64Constant(value(0)),
Int64Constant(value(1))),
MachineRepresentation::kWord64);
Capture<Node*> shl;
Matcher<Node*> shl_matcher = IsWord32PairShl(
IsInt32Constant(low_word_value(0)), IsInt32Constant(high_word_value(0)),
IsInt32Constant(low_word_value(1)));
EXPECT_THAT(graph()->end()->InputAt(1),
IsReturn2(IsProjection(0, AllOf(CaptureEq(&shl), shl_matcher)),
IsProjection(1, AllOf(CaptureEq(&shl), shl_matcher)),
start(), start()));
}
// kExprI64ShrU:
// kExprI64ShrS:
// kExprI64Eq:

46
test/unittests/compiler/node-test-utils.cc
View File

@ -1406,6 +1406,42 @@ class IsLoadContextMatcher final : public NodeMatcher {
const Matcher<Node*> context_matcher_;
};
class IsTernopMatcher final : public NodeMatcher {
public:
IsTernopMatcher(IrOpcode::Value opcode, const Matcher<Node*>& lhs_matcher,
const Matcher<Node*>& mid_matcher,
const Matcher<Node*>& rhs_matcher)
: NodeMatcher(opcode),
lhs_matcher_(lhs_matcher),
mid_matcher_(mid_matcher),
rhs_matcher_(rhs_matcher) {}
void DescribeTo(std::ostream* os) const final {
NodeMatcher::DescribeTo(os);
*os << " whose lhs (";
lhs_matcher_.DescribeTo(os);
*os << ") and mid (";
mid_matcher_.DescribeTo(os);
*os << ") and rhs (";
rhs_matcher_.DescribeTo(os);
*os << ")";
}
bool MatchAndExplain(Node* node, MatchResultListener* listener) const final {
return (NodeMatcher::MatchAndExplain(node, listener) &&
PrintMatchAndExplain(NodeProperties::GetValueInput(node, 0), "lhs",
lhs_matcher_, listener) &&
PrintMatchAndExplain(NodeProperties::GetValueInput(node, 1), "mid",
mid_matcher_, listener) &&
PrintMatchAndExplain(NodeProperties::GetValueInput(node, 2), "rhs",
rhs_matcher_, listener));
}
private:
const Matcher<Node*> lhs_matcher_;
const Matcher<Node*> mid_matcher_;
const Matcher<Node*> rhs_matcher_;
};
class IsBinopMatcher final : public NodeMatcher {
public:
@ -1484,7 +1520,6 @@ class IsParameterMatcher final : public NodeMatcher {
} // namespace
Matcher<Node*> IsDead() {
return MakeMatcher(new NodeMatcher(IrOpcode::kDead));
}
@ -2069,6 +2104,15 @@ Matcher<Node*> IsLoadFramePointer() {
return MakeMatcher(new NodeMatcher(IrOpcode::kLoadFramePointer));
}
#define IS_TERNOP_MATCHER(Name) \
Matcher<Node*> Is##Name(const Matcher<Node*>& lhs_matcher, \
const Matcher<Node*>& mid_matcher, \
const Matcher<Node*>& rhs_matcher) { \
return MakeMatcher(new IsTernopMatcher(IrOpcode::k##Name, lhs_matcher, \
mid_matcher, rhs_matcher)); \
}
IS_TERNOP_MATCHER(Word32PairShl)
#define IS_BINOP_MATCHER(Name) \
Matcher<Node*> Is##Name(const Matcher<Node*>& lhs_matcher, \

4
test/unittests/compiler/node-test-utils.h
View File

@ -358,6 +358,10 @@ Matcher<Node*> IsNumberToUint32(const Matcher<Node*>& input_matcher);
Matcher<Node*> IsParameter(const Matcher<int> index_matcher);
Matcher<Node*> IsLoadFramePointer();
Matcher<Node*> IsWord32PairShl(const Matcher<Node*>& lhs_matcher,
const Matcher<Node*>& mid_matcher,
const Matcher<Node*>& rhs_matcher);
} // namespace compiler
} // namespace internal
} // namespace v8