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[wasm-simd][x64] Check for register when emitting shuffles

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Some shuffles take have either register or memory operand for second
input, but the codegen incorrectly assumes that it is always a register.

Bug: v8:10824
Change-Id: Ia2df233dad4ed451e52e57e35cce5c80db0905db
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2373586
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#69562}
This commit is contained in:
Ng Zhi An 2020-08-25 10:15:47 -07:00 committed by Commit Bot
parent 0834d2e6cf
commit ddf30bea13
3 changed files with 13 additions and 4 deletions
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4
src/codegen/x64/assembler-x64.h
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@ -1646,6 +1646,10 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);

12
src/compiler/backend/x64/code-generator-x64.cc
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@ -667,10 +667,14 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen,
ASSEMBLE_SIMD_INSTR(opcode, dst, input_index); \
} while (false)
#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \
do { \
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
__ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \
#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \
do { \
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
if (instr->InputAt(1)->IsSimd128Register()) { \
__ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \
} else { \
__ opcode(i.OutputSimd128Register(), i.InputOperand(1), imm); \
} \
} while (false)
#define ASSEMBLE_SIMD_ALL_TRUE(opcode) \

1
test/cctest/test-disasm-x64.cc
View File

@ -817,6 +817,7 @@ TEST(DisasmX64) {
__ vpblendw(xmm1, xmm2, xmm3, 23);
__ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);
__ vpalignr(xmm1, xmm2, xmm3, 4);
__ vpalignr(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 4);
__ vblendvpd(xmm1, xmm2, xmm3, xmm4);