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[riscv] Fix qfma test fail

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Change-Id: Ie61c0312e1a4da1f7408e30a61732c8bc6520c7d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4114558
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#84921}
This commit is contained in:
Lu Yahan 2022-12-17 16:40:09 +08:00 committed by V8 LUCI CQ
parent e2a9b050cf
commit e4b6eaf837
2 changed files with 24 additions and 16 deletions
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24
src/compiler/backend/riscv/code-generator-riscv.cc
View File

@ -3264,16 +3264,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kRiscvF64x2Qfma: {
__ VU.set(kScratchReg, E64, m1);
__ vfmadd_vv(i.InputSimd128Register(1), i.InputSimd128Register(2),
i.InputSimd128Register(0));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ vfmadd_vv(i.InputSimd128Register(0), i.InputSimd128Register(1),
i.InputSimd128Register(2));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kRiscvF64x2Qfms: {
__ VU.set(kScratchReg, E64, m1);
__ vfnmsub_vv(i.InputSimd128Register(1), i.InputSimd128Register(2),
i.InputSimd128Register(0));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ vfnmsub_vv(i.InputSimd128Register(0), i.InputSimd128Register(1),
i.InputSimd128Register(2));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kRiscvF32x4ExtractLane: {
@ -3452,16 +3452,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kRiscvF32x4Qfma: {
__ VU.set(kScratchReg, E32, m1);
__ vfmadd_vv(i.InputSimd128Register(1), i.InputSimd128Register(2),
i.InputSimd128Register(0));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ vfmadd_vv(i.InputSimd128Register(0), i.InputSimd128Register(1),
i.InputSimd128Register(2));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kRiscvF32x4Qfms: {
__ VU.set(kScratchReg, E32, m1);
__ vfnmsub_vv(i.InputSimd128Register(1), i.InputSimd128Register(2),
i.InputSimd128Register(0));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ vfnmsub_vv(i.InputSimd128Register(0), i.InputSimd128Register(1),
i.InputSimd128Register(2));
__ vmv_vv(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kRiscvI64x2SConvertI32x4Low: {

16
src/wasm/baseline/riscv/liftoff-assembler-riscv.h
View File

@ -2062,28 +2062,36 @@ void LiftoffAssembler::emit_f32x4_qfma(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister src3) {
bailout(kRelaxedSimd, "emit_f32x4_qfma");
VU.set(kScratchReg, E32, m1);
vfmadd_vv(src1.fp().toV(), src2.fp().toV(), src3.fp().toV());
vmv_vv(dst.fp().toV(), src1.fp().toV());
}
void LiftoffAssembler::emit_f32x4_qfms(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister src3) {
bailout(kRelaxedSimd, "emit_f32x4_qfms");
VU.set(kScratchReg, E32, m1);
vfnmsub_vv(src1.fp().toV(), src2.fp().toV(), src3.fp().toV());
vmv_vv(dst.fp().toV(), src1.fp().toV());
}
void LiftoffAssembler::emit_f64x2_qfma(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister src3) {
bailout(kRelaxedSimd, "emit_f64x2_qfma");
VU.set(kScratchReg, E64, m1);
vfmadd_vv(src1.fp().toV(), src2.fp().toV(), src3.fp().toV());
vmv_vv(dst.fp().toV(), src1.fp().toV());
}
void LiftoffAssembler::emit_f64x2_qfms(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister src3) {
bailout(kRelaxedSimd, "emit_f64x2_qfms");
VU.set(kScratchReg, E64, m1);
vfnmsub_vv(src1.fp().toV(), src2.fp().toV(), src3.fp().toV());
vmv_vv(dst.fp().toV(), src1.fp().toV());
}
void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {