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MIPS: Fix for Ins macro-assembler instruction for non-mips32r2 platforms.

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BUG=
TEST=

Review URL: http://codereview.chromium.org/8520023
Patch from Gergely Kis <gergely@homejinni.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10015 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
danno@chromium.org 2011-11-17 13:31:26 +00:00
parent cfc54e4dac
commit e99b92723d
1 changed files with 10 additions and 23 deletions
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33
src/mips/macro-assembler-mips.cc
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@ -910,34 +910,21 @@ void MacroAssembler::Ins(Register rt,
uint16_t pos,
uint16_t size) {
ASSERT(pos < 32);
ASSERT(pos + size < 32);
ASSERT(pos + size <= 32);
ASSERT(size != 0);
if (mips32r2) {
ins_(rt, rs, pos, size);
} else {
ASSERT(!rt.is(t8) && !rs.is(t8));
srl(t8, rt, pos + size);
// The left chunk from rt that needs to
// be saved is on the right side of t8.
sll(at, t8, pos + size);
// The 'at' register now contains the left chunk on
// the left (proper position) and zeroes.
sll(t8, rt, 32 - pos);
// t8 now contains the right chunk on the left and zeroes.
srl(t8, t8, 32 - pos);
// t8 now contains the right chunk on
// the right (proper position) and zeroes.
or_(rt, at, t8);
// rt now contains the left and right chunks from the original rt
// in their proper position and zeroes in the middle.
sll(t8, rs, 32 - size);
// t8 now contains the chunk from rs on the left and zeroes.
srl(t8, t8, 32 - size - pos);
// t8 now contains the original chunk from rs in
// the middle (proper position).
or_(rt, rt, t8);
// rt now contains the result of the ins instruction in R2 mode.
Subu(at, zero_reg, Operand(1));
srl(at, at, 32 - size);
and_(t8, rs, at);
sll(t8, t8, pos);
sll(at, at, pos);
nor(at, at, zero_reg);
and_(at, rt, at);
or_(rt, t8, at);
}
}