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[mips64][codegen] Fix the case that register rd is the same as rs in Shr and Sar

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The OutputRegister shouldn't be overwritten, because it may be the same register
as InputRegister(1), which will be used later.

And remove the useless if-else in And32, Or32, Xor32.

Change-Id: I1f944b5b6acd5c183cef537524827b47a8cb0186
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1967092
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65438}
This commit is contained in:
Zhao Jiazhong 2019-12-13 03:58:49 -05:00 committed by Commit Bot
parent 3d0a0a8504
commit e99f6ffef3
1 changed files with 4 additions and 19 deletions
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23
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -1094,25 +1094,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
case kMips64And32:
if (instr->InputAt(1)->IsRegister()) {
__ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
} else {
__ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
}
break;
case kMips64Or:
__ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
case kMips64Or32:
if (instr->InputAt(1)->IsRegister()) {
__ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
} else {
__ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
}
break;
case kMips64Nor:
if (instr->InputAt(1)->IsRegister()) {
@ -1136,13 +1126,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
case kMips64Xor32:
if (instr->InputAt(1)->IsRegister()) {
__ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
} else {
__ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
__ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
}
break;
case kMips64Clz:
__ Clz(i.OutputRegister(), i.InputRegister(0));
@ -1181,8 +1166,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
case kMips64Shr:
if (instr->InputAt(1)->IsRegister()) {
__ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
__ srlv(i.OutputRegister(), i.OutputRegister(), i.InputRegister(1));
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
__ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
@ -1192,8 +1177,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
case kMips64Sar:
if (instr->InputAt(1)->IsRegister()) {
__ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
__ srav(i.OutputRegister(), i.OutputRegister(), i.InputRegister(1));
__ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
__ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
} else {
int64_t imm = i.InputOperand(1).immediate();
__ sll(i.OutputRegister(), i.InputRegister(0), 0x0);