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[turbofan] support all shift operands on ia32

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R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/619663002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24387 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
dcarney@chromium.org 2014-10-02 09:04:04 +00:00
parent 5899cc8ca7
commit e9fcaa4be9
5 changed files with 26 additions and 20 deletions
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18
src/compiler/ia32/code-generator-ia32.cc
View File

@ -33,8 +33,6 @@ class IA32OperandConverter : public InstructionOperandConverter {
Operand OutputOperand() { return ToOperand(instr_->Output()); }
Operand TempOperand(int index) { return ToOperand(instr_->TempAt(index)); }
Operand ToOperand(InstructionOperand* op, int extra = 0) {
if (op->IsRegister()) {
DCHECK(extra == 0);
@ -283,30 +281,30 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
case kIA32Shl:
if (HasImmediateInput(instr, 1)) {
__ shl(i.OutputRegister(), i.InputInt5(1));
__ shl(i.OutputOperand(), i.InputInt5(1));
} else {
__ shl_cl(i.OutputRegister());
__ shl_cl(i.OutputOperand());
}
break;
case kIA32Shr:
if (HasImmediateInput(instr, 1)) {
__ shr(i.OutputRegister(), i.InputInt5(1));
__ shr(i.OutputOperand(), i.InputInt5(1));
} else {
__ shr_cl(i.OutputRegister());
__ shr_cl(i.OutputOperand());
}
break;
case kIA32Sar:
if (HasImmediateInput(instr, 1)) {
__ sar(i.OutputRegister(), i.InputInt5(1));
__ sar(i.OutputOperand(), i.InputInt5(1));
} else {
__ sar_cl(i.OutputRegister());
__ sar_cl(i.OutputOperand());
}
break;
case kIA32Ror:
if (HasImmediateInput(instr, 1)) {
__ ror(i.OutputRegister(), i.InputInt5(1));
__ ror(i.OutputOperand(), i.InputInt5(1));
} else {
__ ror_cl(i.OutputRegister());
__ ror_cl(i.OutputOperand());
}
break;
case kSSEFloat64Cmp:

5
src/compiler/ia32/instruction-selector-ia32.cc
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@ -329,9 +329,8 @@ static inline void VisitShift(InstructionSelector* selector, Node* node,
Node* left = node->InputAt(0);
Node* right = node->InputAt(1);
// TODO(turbofan): assembler only supports some addressing modes for shifts.
if (g.CanBeImmediate(right)) {
selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseImmediate(right));
} else {
Int32BinopMatcher m(node);
@ -341,7 +340,7 @@ static inline void VisitShift(InstructionSelector* selector, Node* node,
right = mright.left().node();
}
}
selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
selector->Emit(opcode, g.DefineSameAsFirst(node), g.Use(left),
g.UseFixed(right, ecx));
}
}

10
src/ia32/assembler-ia32.cc
View File

@ -982,24 +982,24 @@ void Assembler::rcr(Register dst, uint8_t imm8) {
}
void Assembler::ror(Register dst, uint8_t imm8) {
void Assembler::ror(const Operand& dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
EMIT(0xD1);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
} else {
EMIT(0xC1);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
EMIT(imm8);
}
}
void Assembler::ror_cl(Register dst) {
void Assembler::ror_cl(const Operand& dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
EMIT(0xC8 | dst.code());
emit_operand(ecx, dst);
}

7
src/ia32/assembler-ia32.h
View File

@ -740,8 +740,11 @@ class Assembler : public AssemblerBase {
void rcl(Register dst, uint8_t imm8);
void rcr(Register dst, uint8_t imm8);
void ror(Register dst, uint8_t imm8);
void ror_cl(Register dst);
void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
void ror(const Operand& dst, uint8_t imm8);
void ror_cl(Register dst) { ror_cl(Operand(dst)); }
void ror_cl(const Operand& dst);
void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
void sar(const Operand& dst, uint8_t imm8);

6
test/cctest/test-disasm-ia32.cc
View File

@ -201,6 +201,12 @@ TEST(DisasmIa320) {
__ rcl(edx, 7);
__ rcr(edx, 1);
__ rcr(edx, 7);
__ ror(edx, 1);
__ ror(edx, 6);
__ ror_cl(edx);
__ ror(Operand(ebx, ecx, times_4, 10000), 1);
__ ror(Operand(ebx, ecx, times_4, 10000), 6);
__ ror_cl(Operand(ebx, ecx, times_4, 10000));
__ sar(edx, 1);
__ sar(edx, 6);
__ sar_cl(edx);