Add miscellaneous operations to x64 assembler.
Review URL: http://codereview.chromium.org/113997 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2089 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
whesse@chromium.org
parent
8c78e673ad
commit
ea0644506d
@ -36,6 +36,10 @@ namespace internal {
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class Memory {
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public:
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static uint16_t& uint16_at(Address addr) {
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return *reinterpret_cast<uint16_t*>(addr);
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}
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static uint32_t& uint32_at(Address addr) {
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return *reinterpret_cast<uint32_t*>(addr);
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}
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@ -55,6 +55,12 @@ void Assembler::emitq(uint64_t x, RelocInfo::Mode rmode) {
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}
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void Assembler::emitw(uint16_t x) {
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Memory::uint16_at(pc_) = x;
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pc_ += sizeof(uint16_t);
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}
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// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
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// REX.W is set. REX.X is cleared.
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void Assembler::emit_rex_64(Register reg, Register rm_reg) {
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@ -118,14 +124,14 @@ void Assembler::emit_optional_rex_32(Register reg, const Operand& op) {
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}
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void Assembler::set_target_address_at(byte* location, byte* value) {
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UNIMPLEMENTED();
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Address Assembler::target_address_at(Address pc) {
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return Memory::Address_at(pc);
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}
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byte* Assembler::target_address_at(byte* location) {
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UNIMPLEMENTED();
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return NULL;
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void Assembler::set_target_address_at(Address pc, Address target) {
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Memory::Address_at(pc) = target;
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CPU::FlushICache(pc, sizeof(intptr_t));
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}
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@ -166,6 +172,8 @@ void RelocInfo::set_target_address(Address target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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Assembler::set_target_address_at(pc_, target);
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}
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Object* RelocInfo::target_object() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return *reinterpret_cast<Object**>(pc_);
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@ -77,7 +77,73 @@ uint64_t CpuFeatures::supported_ = 0;
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uint64_t CpuFeatures::enabled_ = 0;
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void CpuFeatures::Probe() {
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// TODO(X64): UNIMPLEMENTED
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ASSERT(Heap::HasBeenSetup());
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ASSERT(supported_ == 0);
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if (Serializer::enabled()) return; // No features if we might serialize.
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Assembler assm(NULL, 0);
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Label cpuid, done;
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#define __ assm.
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// Save old esp, since we are going to modify the stack.
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__ push(rbp);
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__ pushfq();
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__ push(rcx);
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__ push(rbx);
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__ movq(rbp, rsp);
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// If we can modify bit 21 of the EFLAGS register, then CPUID is supported.
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__ pushfq();
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__ pop(rax);
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__ movq(rdx, rax);
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__ xor_(rax, Immediate(0x200000)); // Flip bit 21.
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__ push(rax);
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__ popfq();
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__ pushfq();
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__ pop(rax);
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__ xor_(rax, rdx); // Different if CPUID is supported.
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__ j(not_zero, &cpuid);
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// CPUID not supported. Clear the supported features in edx:eax.
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__ xor_(rax, rax);
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__ jmp(&done);
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// Invoke CPUID with 1 in eax to get feature information in
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// ecx:edx. Temporarily enable CPUID support because we know it's
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// safe here.
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__ bind(&cpuid);
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__ movq(rax, Immediate(1));
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supported_ = (1 << CPUID);
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{ Scope fscope(CPUID);
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__ cpuid();
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}
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supported_ = 0;
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// Move the result from ecx:edx to rax and make sure to mark the
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// CPUID feature as supported.
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__ movl(rax, rdx); // Zero-extended to 64 bits.
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__ shl(rcx, Immediate(32));
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__ or_(rax, rcx);
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__ or_(rax, Immediate(1 << CPUID));
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// Done.
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__ bind(&done);
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__ movq(rsp, rbp);
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__ pop(rbx);
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__ pop(rcx);
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__ popfq();
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__ pop(rbp);
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__ ret(0);
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#undef __
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CodeDesc desc;
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assm.GetCode(&desc);
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Object* code =
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Heap::CreateCode(desc, NULL, Code::ComputeFlags(Code::STUB), NULL);
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if (!code->IsCode()) return;
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LOG(CodeCreateEvent("Builtin", Code::cast(code), "CpuFeatures::Probe"));
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typedef uint64_t (*F0)();
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F0 probe = FUNCTION_CAST<F0>(Code::cast(code)->entry());
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supported_ = probe();
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}
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// -----------------------------------------------------------------------------
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@ -368,6 +434,26 @@ void Assembler::shift(Register dst, int subcode) {
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}
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void Assembler::bt(const Operand& dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_rex_64(src, dst);
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emit(0x0F);
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emit(0xA3);
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emit_operand(src, dst);
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}
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void Assembler::bts(const Operand& dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_rex_64(src, dst);
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emit(0x0F);
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emit(0xAB);
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emit_operand(src, dst);
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}
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void Assembler::call(Label* L) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -401,6 +487,23 @@ void Assembler::call(Register adr) {
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}
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void Assembler::cpuid() {
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ASSERT(CpuFeatures::IsEnabled(CpuFeatures::CPUID));
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit(0x0F);
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emit(0xA2);
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}
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void Assembler::cqo() {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_rex_64();
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emit(0x99);
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}
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void Assembler::dec(Register dst) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -419,6 +522,15 @@ void Assembler::dec(const Operand& dst) {
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}
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void Assembler::enter(Immediate size) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit(0xC8);
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emitw(size.value_); // 16 bit operand, always.
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emit(0);
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}
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void Assembler::hlt() {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -530,6 +642,49 @@ void Assembler::jmp(Register target) {
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}
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void Assembler::lea(Register dst, const Operand& src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_rex_64(dst, src);
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emit(0x8D);
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emit_operand(dst, src);
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}
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void Assembler::leave() {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit(0xC9);
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}
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void Assembler::movl(Register dst, const Operand& src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_optional_rex_32(dst, src);
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emit(0x8B);
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emit_operand(dst, src);
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}
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void Assembler::movl(Register dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_optional_rex_32(dst, src);
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emit(0x8B);
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emit(0xC0 | (dst.code() & 0x7) << 3 | (src.code() & 0x7));
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}
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void Assembler::movl(const Operand& dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_optional_rex_32(src, dst);
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emit(0x89);
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emit_operand(src, dst);
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}
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void Assembler::movq(Register dst, const Operand& src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -548,6 +703,15 @@ void Assembler::movq(Register dst, Register src) {
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}
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void Assembler::movq(const Operand& dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit_rex_64(src, dst);
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emit(0x89);
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emit_operand(src, dst);
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}
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void Assembler::movq(Register dst, Immediate value) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -716,6 +880,13 @@ void Assembler::pop(const Operand& dst) {
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}
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void Assembler::popfq() {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit(0x9D);
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}
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void Assembler::push(Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -735,6 +906,43 @@ void Assembler::push(const Operand& src) {
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}
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void Assembler::push(Immediate value) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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if (is_int8(value.value_)) {
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emit(0x6A);
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emit(value.value_); // Emit low byte of value.
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} else {
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emit(0x68);
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emitl(value.value_);
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}
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}
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void Assembler::pushfq() {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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emit(0x9C);
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}
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void Assembler::rcl(Register dst, uint8_t imm8) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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ASSERT(is_uint6(imm8)); // illegal shift count
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if (imm8 == 1) {
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emit_rex_64(dst);
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emit(0xD1);
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emit(0xD0 | (dst.code() & 0x7));
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} else {
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emit_rex_64(dst);
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emit(0xC1);
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emit(0xD0 | (dst.code() & 0x7));
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emit(imm8);
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}
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}
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void Assembler::ret(int imm16) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -749,6 +957,21 @@ void Assembler::ret(int imm16) {
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}
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void Assembler::xchg(Register dst, Register src) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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if (src.is(rax) || dst.is(rax)) { // Single-byte encoding
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Register other = src.is(rax) ? dst : src;
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emit_rex_64(other);
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emit(0x90 | (other.code() & 0x7));
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} else {
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emit_rex_64(src, dst);
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emit(0x87);
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emit(0xC0 | (src.code() & 0x7) << 3 | (dst.code() & 0x7));
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}
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}
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void Assembler::testb(Register reg, Immediate mask) {
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EnsureSpace ensure_space(this);
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last_pc_ = pc_;
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@ -294,11 +294,11 @@ class CpuFeatures : public AllStatic {
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static void Probe();
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// Check whether a feature is supported by the target CPU.
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static bool IsSupported(Feature f) {
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return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
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return (supported_ & (V8_UINT64_C(1) << f)) != 0;
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}
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// Check whether a feature is currently enabled.
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static bool IsEnabled(Feature f) {
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return (enabled_ & (static_cast<uint64_t>(1) << f)) != 0;
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return (enabled_ & (V8_UINT64_C(1) << f)) != 0;
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}
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// Enable a specified feature within a scope.
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class Scope BASE_EMBEDDED {
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@ -307,7 +307,7 @@ class CpuFeatures : public AllStatic {
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explicit Scope(Feature f) {
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ASSERT(CpuFeatures::IsSupported(f));
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old_enabled_ = CpuFeatures::enabled_;
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CpuFeatures::enabled_ |= (static_cast<uint64_t>(1) << f);
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CpuFeatures::enabled_ |= (V8_UINT64_C(1) << f);
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}
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~Scope() { CpuFeatures::enabled_ = old_enabled_; }
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private:
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@ -355,8 +355,9 @@ class Assembler : public Malloced {
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void GetCode(CodeDesc* desc);
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// Read/Modify the code target in the branch/call instruction at pc.
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inline static Address target_address_at(Address pc);
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inline static void set_target_address_at(Address pc, Address target);
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// On the x64 architecture, the address is absolute, not relative.
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static inline Address target_address_at(Address pc);
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static inline void set_target_address_at(Address pc, Address target);
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// Distance between the address of the code target in the call instruction
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// and the return address
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@ -387,13 +388,10 @@ class Assembler : public Malloced {
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void Align(int m);
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// Stack
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void pushad();
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void popad();
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void pushfq();
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void popfq();
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void pushfd();
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void popfd();
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void push(const Immediate& x);
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void push(Immediate value);
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void push(Register src);
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void push(const Operand& src);
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void push(Label* label, RelocInfo::Mode relocation_mode);
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@ -401,7 +399,7 @@ class Assembler : public Malloced {
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void pop(Register dst);
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void pop(const Operand& dst);
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void enter(const Immediate& size);
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void enter(Immediate size);
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void leave();
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// Moves
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@ -409,6 +407,10 @@ class Assembler : public Malloced {
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void movb(const Operand& dst, int8_t imm8);
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void movb(const Operand& dst, Register src);
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void movl(Register dst, Register src);
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void movl(Register dst, const Operand& src);
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void movl(const Operand& dst, Register src);
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void movq(Register dst, int32_t imm32);
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void movq(Register dst, Immediate x);
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void movq(Register dst, const Operand& src);
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@ -515,7 +517,8 @@ class Assembler : public Malloced {
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void dec(Register dst);
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void dec(const Operand& dst);
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void cdq();
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// Sign-extends rax into rdx:rax.
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void cqo();
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void idiv(Register src);
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@ -830,6 +833,7 @@ class Assembler : public Malloced {
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inline void emitl(uint32_t x);
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inline void emit(Handle<Object> handle);
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inline void emitq(uint64_t x, RelocInfo::Mode rmode);
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inline void emitw(uint16_t x);
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void emit(Immediate x) { emitl(x.value_); }
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// Emits a REX prefix that encodes a 64-bit operand size and
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@ -858,6 +862,9 @@ class Assembler : public Malloced {
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// REX.W is set and REX.R clear.
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inline void emit_rex_64(const Operand& op);
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// Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
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void emit_rex_64() { emit(0x48); }
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// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
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// REX.W is clear.
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inline void emit_rex_32(Register reg, Register rm_reg);
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