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[wasm-simd] Implement i64x2 add sub for arm

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Also some cleanup reordering of instruction codes.

Bug: v8:9813
Change-Id: I35caad0b84dd5824090046cba964454eac45d5d8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1925613
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65088}
This commit is contained in:
Ng Zhi An 2019-11-19 15:33:29 -08:00 committed by Commit Bot
parent aafbc13834
commit ea06b01e52
7 changed files with 32 additions and 20 deletions
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10
src/compiler/backend/arm/code-generator-arm.cc
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@ -1923,6 +1923,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ReplaceLane(dst, dst, i.InputRegister(3), NeonS32, lane * 2 + 1);
break;
}
case kArmI64x2Add: {
__ vadd(Neon64, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI64x2Sub: {
__ vsub(Neon64, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI64x2Neg: {
Simd128Register dst = i.OutputSimd128Register();
__ vmov(dst, static_cast<uint64_t>(0));

14
src/compiler/backend/arm/instruction-codes-arm.h
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@ -142,12 +142,6 @@ namespace compiler {
V(ArmF64x2Ne) \
V(ArmF64x2Lt) \
V(ArmF64x2Le) \
V(ArmI64x2SplatI32Pair) \
V(ArmI64x2ReplaceLaneI32Pair) \
V(ArmI64x2Neg) \
V(ArmI64x2Shl) \
V(ArmI64x2ShrS) \
V(ArmI64x2ShrU) \
V(ArmF32x4Splat) \
V(ArmF32x4ExtractLane) \
V(ArmF32x4ReplaceLane) \
@ -169,6 +163,14 @@ namespace compiler {
V(ArmF32x4Ne) \
V(ArmF32x4Lt) \
V(ArmF32x4Le) \
V(ArmI64x2SplatI32Pair) \
V(ArmI64x2ReplaceLaneI32Pair) \
V(ArmI64x2Neg) \
V(ArmI64x2Shl) \
V(ArmI64x2ShrS) \
V(ArmI64x2Add) \
V(ArmI64x2Sub) \
V(ArmI64x2ShrU) \
V(ArmI32x4Splat) \
V(ArmI32x4ExtractLane) \
V(ArmI32x4ReplaceLane) \

14
src/compiler/backend/arm/instruction-scheduler-arm.cc
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@ -122,12 +122,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmF64x2Ne:
case kArmF64x2Lt:
case kArmF64x2Le:
case kArmI64x2SplatI32Pair:
case kArmI64x2ReplaceLaneI32Pair:
case kArmI64x2Neg:
case kArmI64x2Shl:
case kArmI64x2ShrS:
case kArmI64x2ShrU:
case kArmF32x4Splat:
case kArmF32x4ExtractLane:
case kArmF32x4ReplaceLane:
@ -149,6 +143,14 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmF32x4Ne:
case kArmF32x4Lt:
case kArmF32x4Le:
case kArmI64x2SplatI32Pair:
case kArmI64x2ReplaceLaneI32Pair:
case kArmI64x2Neg:
case kArmI64x2Shl:
case kArmI64x2ShrS:
case kArmI64x2Add:
case kArmI64x2Sub:
case kArmI64x2ShrU:
case kArmI32x4Splat:
case kArmI32x4ExtractLane:
case kArmI32x4ReplaceLane:

2
src/compiler/backend/arm/instruction-selector-arm.cc
View File

@ -2463,6 +2463,8 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
V(F32x4Ne, kArmF32x4Ne) \
V(F32x4Lt, kArmF32x4Lt) \
V(F32x4Le, kArmF32x4Le) \
V(I64x2Add, kArmI64x2Add) \
V(I64x2Sub, kArmI64x2Sub) \
V(I32x4Add, kArmI32x4Add) \
V(I32x4AddHoriz, kArmI32x4AddHoriz) \
V(I32x4Sub, kArmI32x4Sub) \

2
src/compiler/backend/instruction-selector.cc
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@ -2625,8 +2625,6 @@ void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
#if !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitF64x2Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Mul(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitI64x2Splat(Node* node) { UNIMPLEMENTED(); }

8
src/execution/arm/simulator-arm.cc
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@ -4395,8 +4395,8 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
case Neon32:
Add<uint32_t, kSimd128Size>(this, Vd, Vm, Vn);
break;
default:
UNREACHABLE();
case Neon64:
Add<uint64_t, kSimd128Size>(this, Vd, Vm, Vn);
break;
}
} else {
@ -4828,8 +4828,8 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
case Neon32:
Sub<uint32_t, kSimd128Size>(this, Vd, Vm, Vn);
break;
default:
UNREACHABLE();
case Neon64:
Sub<uint64_t, kSimd128Size>(this, Vd, Vm, Vn);
break;
}
} else {

2
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -1024,7 +1024,6 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2ShrU) {
LogicalShiftRight);
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_IA32
void RunI64x2BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int64BinOp expected_op) {
WasmRunner<int32_t, int64_t, int64_t> r(execution_tier, lower_simd);
@ -1104,7 +1103,6 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2GeU) {
UnsignedGreaterEqual);
}
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_IA32
WASM_SIMD_TEST_NO_LOWERING(F64x2Splat) {
WasmRunner<int32_t, double> r(execution_tier, lower_simd);