From ea0a1561c1f32d308e8309df72d9870201d9b34e Mon Sep 17 00:00:00 2001 From: Milad Farazmand Date: Tue, 9 Jun 2020 13:59:52 +0000 Subject: [PATCH] PPC: [wasm-simd] Implement simd comparisons Change-Id: I782f5b0dd8ed374df406fb615f6e74efed8b5368 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2235658 Reviewed-by: Junliang Yan Commit-Queue: Milad Farazmand Cr-Commit-Position: refs/heads/master@{#68267} --- src/codegen/ppc/assembler-ppc.h | 15 ++ .../backend/ppc/code-generator-ppc.cc | 200 ++++++++++++++++++ .../backend/ppc/instruction-codes-ppc.h | 32 +++ .../backend/ppc/instruction-scheduler-ppc.cc | 32 +++ .../backend/ppc/instruction-selector-ppc.cc | 80 +++---- 5 files changed, 306 insertions(+), 53 deletions(-) diff --git a/src/codegen/ppc/assembler-ppc.h b/src/codegen/ppc/assembler-ppc.h index 906314845f..d8f1d8ef20 100644 --- a/src/codegen/ppc/assembler-ppc.h +++ b/src/codegen/ppc/assembler-ppc.h @@ -487,6 +487,21 @@ class Assembler : public AssemblerBase { PPC_VA_OPCODE_A_FORM_LIST(DECLARE_PPC_VA_INSTRUCTIONS_A_FORM) #undef DECLARE_PPC_VA_INSTRUCTIONS_A_FORM +#define DECLARE_PPC_VC_INSTRUCTIONS(name, instr_name, instr_value) \ + inline void name(const Simd128Register rt, const Simd128Register ra, \ + const Simd128Register rb, const RCBit rc = LeaveRC) { \ + vc_form(instr_name, rt, ra, rb, rc); \ + } + + inline void vc_form(Instr instr, Simd128Register rt, Simd128Register ra, + Simd128Register rb, int rc) { + emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 | + rc * B10); + } + + PPC_VC_OPCODE_LIST(DECLARE_PPC_VC_INSTRUCTIONS) +#undef DECLARE_PPC_VC_INSTRUCTIONS + RegList* GetScratchRegisterList() { return &scratch_register_list_; } // --------------------------------------------------------------------------- // Code generation diff --git a/src/compiler/backend/ppc/code-generator-ppc.cc b/src/compiler/backend/ppc/code-generator-ppc.cc index a378c1a4a5..90daf865e3 100644 --- a/src/compiler/backend/ppc/code-generator-ppc.cc +++ b/src/compiler/backend/ppc/code-generator-ppc.cc @@ -2610,6 +2610,206 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( i.InputSimd128Register(1)); break; } + case kPPC_F64x2Eq: { + __ xvcmpeqdp(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_F64x2Ne: { + __ xvcmpeqdp(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_F64x2Le: { + __ xvcmpgedp(i.OutputSimd128Register(), i.InputSimd128Register(1), + i.InputSimd128Register(0)); + break; + } + case kPPC_F64x2Lt: { + __ xvcmpgtdp(i.OutputSimd128Register(), i.InputSimd128Register(1), + i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4Eq: { + __ xvcmpeqsp(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I64x2Eq: { + __ vcmpequd(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I32x4Eq: { + __ vcmpequw(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I16x8Eq: { + __ vcmpequh(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I8x16Eq: { + __ vcmpequb(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_F32x4Ne: { + __ xvcmpeqsp(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_I64x2Ne: { + __ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_I32x4Ne: { + __ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_I16x8Ne: { + __ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_I8x16Ne: { + __ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg); + break; + } + case kPPC_F32x4Lt: { + __ xvcmpgtsp(i.OutputSimd128Register(), i.InputSimd128Register(1), + i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4Le: { + __ xvcmpgesp(i.OutputSimd128Register(), i.InputSimd128Register(1), + i.InputSimd128Register(0)); + break; + } + case kPPC_I64x2GtS: { + __ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I32x4GtS: { + __ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I64x2GeS: { + __ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I32x4GeS: { + __ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I64x2GtU: { + __ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I32x4GtU: { + __ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + + break; + } + case kPPC_I64x2GeU: { + __ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + + break; + } + case kPPC_I32x4GeU: { + __ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I16x8GtS: { + __ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I16x8GeS: { + __ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I16x8GtU: { + __ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I16x8GeU: { + __ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I8x16GtS: { + __ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I8x16GeS: { + __ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } + case kPPC_I8x16GtU: { + __ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } + case kPPC_I8x16GeU: { + __ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + __ vor(i.OutputSimd128Register(), i.OutputSimd128Register(), + kScratchDoubleReg); + break; + } case kPPC_StoreCompressTagged: { ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); break; diff --git a/src/compiler/backend/ppc/instruction-codes-ppc.h b/src/compiler/backend/ppc/instruction-codes-ppc.h index 888841c947..90c66d82fb 100644 --- a/src/compiler/backend/ppc/instruction-codes-ppc.h +++ b/src/compiler/backend/ppc/instruction-codes-ppc.h @@ -196,6 +196,10 @@ namespace compiler { V(PPC_F64x2Add) \ V(PPC_F64x2Sub) \ V(PPC_F64x2Mul) \ + V(PPC_F64x2Eq) \ + V(PPC_F64x2Ne) \ + V(PPC_F64x2Le) \ + V(PPC_F64x2Lt) \ V(PPC_F32x4Splat) \ V(PPC_F32x4ExtractLane) \ V(PPC_F32x4ReplaceLane) \ @@ -203,6 +207,10 @@ namespace compiler { V(PPC_F32x4AddHoriz) \ V(PPC_F32x4Sub) \ V(PPC_F32x4Mul) \ + V(PPC_F32x4Eq) \ + V(PPC_F32x4Ne) \ + V(PPC_F32x4Lt) \ + V(PPC_F32x4Le) \ V(PPC_I64x2Splat) \ V(PPC_I64x2ExtractLane) \ V(PPC_I64x2ReplaceLane) \ @@ -213,6 +221,12 @@ namespace compiler { V(PPC_I64x2MinU) \ V(PPC_I64x2MaxS) \ V(PPC_I64x2MaxU) \ + V(PPC_I64x2Eq) \ + V(PPC_I64x2Ne) \ + V(PPC_I64x2GtS) \ + V(PPC_I64x2GtU) \ + V(PPC_I64x2GeU) \ + V(PPC_I64x2GeS) \ V(PPC_I32x4Splat) \ V(PPC_I32x4ExtractLane) \ V(PPC_I32x4ReplaceLane) \ @@ -224,6 +238,12 @@ namespace compiler { V(PPC_I32x4MinU) \ V(PPC_I32x4MaxS) \ V(PPC_I32x4MaxU) \ + V(PPC_I32x4Eq) \ + V(PPC_I32x4Ne) \ + V(PPC_I32x4GtS) \ + V(PPC_I32x4GeS) \ + V(PPC_I32x4GtU) \ + V(PPC_I32x4GeU) \ V(PPC_I16x8Splat) \ V(PPC_I16x8ExtractLaneU) \ V(PPC_I16x8ExtractLaneS) \ @@ -236,6 +256,12 @@ namespace compiler { V(PPC_I16x8MinU) \ V(PPC_I16x8MaxS) \ V(PPC_I16x8MaxU) \ + V(PPC_I16x8Eq) \ + V(PPC_I16x8Ne) \ + V(PPC_I16x8GtS) \ + V(PPC_I16x8GeS) \ + V(PPC_I16x8GtU) \ + V(PPC_I16x8GeU) \ V(PPC_I8x16Splat) \ V(PPC_I8x16ExtractLaneU) \ V(PPC_I8x16ExtractLaneS) \ @@ -247,6 +273,12 @@ namespace compiler { V(PPC_I8x16MinU) \ V(PPC_I8x16MaxS) \ V(PPC_I8x16MaxU) \ + V(PPC_I8x16Eq) \ + V(PPC_I8x16Ne) \ + V(PPC_I8x16GtS) \ + V(PPC_I8x16GeS) \ + V(PPC_I8x16GtU) \ + V(PPC_I8x16GeU) \ V(PPC_StoreCompressTagged) \ V(PPC_LoadDecompressTaggedSigned) \ V(PPC_LoadDecompressTaggedPointer) \ diff --git a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc index 788e421352..22fc4209cc 100644 --- a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc +++ b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc @@ -119,6 +119,10 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_F64x2Add: case kPPC_F64x2Sub: case kPPC_F64x2Mul: + case kPPC_F64x2Eq: + case kPPC_F64x2Ne: + case kPPC_F64x2Le: + case kPPC_F64x2Lt: case kPPC_F32x4Splat: case kPPC_F32x4ExtractLane: case kPPC_F32x4ReplaceLane: @@ -126,6 +130,10 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_F32x4AddHoriz: case kPPC_F32x4Sub: case kPPC_F32x4Mul: + case kPPC_F32x4Eq: + case kPPC_F32x4Ne: + case kPPC_F32x4Lt: + case kPPC_F32x4Le: case kPPC_I64x2Splat: case kPPC_I64x2ExtractLane: case kPPC_I64x2ReplaceLane: @@ -136,6 +144,12 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_I64x2MinU: case kPPC_I64x2MaxS: case kPPC_I64x2MaxU: + case kPPC_I64x2Eq: + case kPPC_I64x2Ne: + case kPPC_I64x2GtS: + case kPPC_I64x2GtU: + case kPPC_I64x2GeU: + case kPPC_I64x2GeS: case kPPC_I32x4Splat: case kPPC_I32x4ExtractLane: case kPPC_I32x4ReplaceLane: @@ -147,6 +161,12 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_I32x4MinU: case kPPC_I32x4MaxS: case kPPC_I32x4MaxU: + case kPPC_I32x4Eq: + case kPPC_I32x4Ne: + case kPPC_I32x4GtS: + case kPPC_I32x4GeS: + case kPPC_I32x4GtU: + case kPPC_I32x4GeU: case kPPC_I16x8Splat: case kPPC_I16x8ExtractLaneU: case kPPC_I16x8ExtractLaneS: @@ -159,6 +179,12 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_I16x8MinU: case kPPC_I16x8MaxS: case kPPC_I16x8MaxU: + case kPPC_I16x8Eq: + case kPPC_I16x8Ne: + case kPPC_I16x8GtS: + case kPPC_I16x8GeS: + case kPPC_I16x8GtU: + case kPPC_I16x8GeU: case kPPC_I8x16Splat: case kPPC_I8x16ExtractLaneU: case kPPC_I8x16ExtractLaneS: @@ -170,6 +196,12 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_I8x16MinU: case kPPC_I8x16MaxS: case kPPC_I8x16MaxU: + case kPPC_I8x16Eq: + case kPPC_I8x16Ne: + case kPPC_I8x16GtS: + case kPPC_I8x16GeS: + case kPPC_I8x16GtU: + case kPPC_I8x16GeU: return kNoOpcodeFlags; case kPPC_LoadWordS8: diff --git a/src/compiler/backend/ppc/instruction-selector-ppc.cc b/src/compiler/backend/ppc/instruction-selector-ppc.cc index d779d69ac7..f4e0d0fe90 100644 --- a/src/compiler/backend/ppc/instruction-selector-ppc.cc +++ b/src/compiler/backend/ppc/instruction-selector-ppc.cc @@ -2131,10 +2131,18 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(F64x2Add) \ V(F64x2Sub) \ V(F64x2Mul) \ + V(F64x2Eq) \ + V(F64x2Ne) \ + V(F64x2Le) \ + V(F64x2Lt) \ V(F32x4Add) \ V(F32x4AddHoriz) \ V(F32x4Sub) \ V(F32x4Mul) \ + V(F32x4Eq) \ + V(F32x4Ne) \ + V(F32x4Lt) \ + V(F32x4Le) \ V(I64x2Add) \ V(I64x2Sub) \ V(I64x2Mul) \ @@ -2146,6 +2154,12 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(I32x4MinU) \ V(I32x4MaxS) \ V(I32x4MaxU) \ + V(I32x4Eq) \ + V(I32x4Ne) \ + V(I32x4GtS) \ + V(I32x4GeS) \ + V(I32x4GtU) \ + V(I32x4GeU) \ V(I16x8Add) \ V(I16x8AddHoriz) \ V(I16x8Sub) \ @@ -2154,13 +2168,25 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(I16x8MinU) \ V(I16x8MaxS) \ V(I16x8MaxU) \ + V(I16x8Eq) \ + V(I16x8Ne) \ + V(I16x8GtS) \ + V(I16x8GeS) \ + V(I16x8GtU) \ + V(I16x8GeU) \ V(I8x16Add) \ V(I8x16Sub) \ V(I8x16Mul) \ V(I8x16MinS) \ V(I8x16MinU) \ V(I8x16MaxS) \ - V(I8x16MaxU) + V(I8x16MaxU) \ + V(I8x16Eq) \ + V(I8x16Ne) \ + V(I8x16GtS) \ + V(I8x16GeS) \ + V(I8x16GtU) \ + V(I8x16GeU) #define SIMD_VISIT_SPLAT(Type) \ void InstructionSelector::Visit##Type##Splat(Node* node) { \ @@ -2216,22 +2242,10 @@ void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI32x4Eq(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI32x4Ne(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI32x4GtS(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI32x4GeS(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI32x4GtU(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI32x4GeU(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); } @@ -2246,10 +2260,6 @@ void InstructionSelector::VisitI16x8SubSaturateS(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI16x8AddSaturateU(Node* node) { UNIMPLEMENTED(); } @@ -2260,14 +2270,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) { void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI16x8GeS(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI16x8GtU(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) { UNIMPLEMENTED(); } @@ -2286,14 +2288,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI8x16GtS(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI8x16GeS(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI8x16AddSaturateU(Node* node) { UNIMPLEMENTED(); } @@ -2302,10 +2296,6 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI8x16GtU(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitI8x16GeU(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitS128And(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS128Or(Node* node) { UNIMPLEMENTED(); } @@ -2318,14 +2308,6 @@ void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS128Zero(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitF32x4Eq(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Ne(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Lt(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Le(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::EmitPrepareResults( ZoneVector* results, const CallDescriptor* call_descriptor, Node* node) { @@ -2462,14 +2444,6 @@ void InstructionSelector::VisitF64x2Sqrt(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2Div(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitF64x2Eq(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2Ne(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2Le(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI64x2Shl(Node* node) { UNIMPLEMENTED(); }