PPC [simd]: Implement vand complement, div and QF ops on Sim
Change-Id: I614d1ccf83e1275d06211917906e7094bfad5bc4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2757691 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#73384}
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@ -3989,6 +3989,10 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
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VECTOR_LOGICAL_OP(a_val & b_val)
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break;
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}
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case VANDC: {
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VECTOR_LOGICAL_OP(a_val & (~b_val))
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break;
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}
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case VOR: {
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VECTOR_LOGICAL_OP(a_val | b_val)
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break;
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@ -4022,6 +4026,10 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
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VECTOR_ARITHMETIC_OP(double, *)
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break;
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}
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case XVDIVDP: {
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VECTOR_ARITHMETIC_OP(double, /)
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break;
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}
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case VADDFP: {
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VECTOR_ARITHMETIC_OP(float, +)
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break;
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@ -4034,6 +4042,10 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
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VECTOR_ARITHMETIC_OP(float, *)
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break;
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}
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case XVDIVSP: {
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VECTOR_ARITHMETIC_OP(float, /)
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break;
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}
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case VADDUDM: {
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VECTOR_ARITHMETIC_OP(int64_t, +)
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break;
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@ -4503,6 +4515,35 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
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}
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break;
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}
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#define VECTOR_FP_QF(type, sign) \
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DECODE_VX_INSTRUCTION(t, a, b, T) \
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FOR_EACH_LANE(i, type) { \
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type a_val = get_simd_register_by_lane<type>(a, i); \
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type b_val = get_simd_register_by_lane<type>(b, i); \
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type t_val = get_simd_register_by_lane<type>(t, i); \
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type reuslt = sign * ((sign * b_val) + (a_val * t_val)); \
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if (isinf(a_val)) reuslt = a_val; \
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if (isinf(b_val)) reuslt = b_val; \
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if (isinf(t_val)) reuslt = t_val; \
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set_simd_register_by_lane<type>(t, i, reuslt); \
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}
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case XVMADDMDP: {
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VECTOR_FP_QF(double, +1)
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break;
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}
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case XVNMSUBMDP: {
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VECTOR_FP_QF(double, -1)
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break;
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}
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case XVMADDMSP: {
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VECTOR_FP_QF(float, +1)
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break;
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}
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case XVNMSUBMSP: {
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VECTOR_FP_QF(float, -1)
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break;
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}
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#undef VECTOR_FP_QF
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#undef FOR_EACH_LANE
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#undef DECODE_VX_INSTRUCTION
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default: {
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