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[wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le

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Currently SIMD integer comparison ops are implemented using Lt/Le, this is
sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
clobber the destination register, and will need additional instructions to
when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
as the underlying implementation as this will only require swapping operands
on MIPS and is consistent with x86/ARM instructions.

BUG=v8:6020

R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org

Review-Url: https://codereview.chromium.org/2874403002
Cr-Commit-Position: refs/heads/master@{#45440}
This commit is contained in:
gdeepti 2017-05-21 15:40:46 -07:00 committed by Commit bot
parent 12e6f1cb5c
commit eeefc74a11
15 changed files with 280 additions and 277 deletions
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72
src/compiler/arm/code-generator-arm.cc
View File

@ -1797,14 +1797,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vmvn(dst, dst);
break;
}
case kArmI32x4LtS: {
__ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI32x4GtS: {
__ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI32x4LeS: {
__ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI32x4GeS: {
__ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI32x4UConvertF32x4: {
@ -1836,14 +1836,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kArmI32x4LtU: {
__ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI32x4GtU: {
__ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI32x4LeU: {
__ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI32x4GeU: {
__ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI16x8Splat: {
@ -1937,14 +1937,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vmvn(dst, dst);
break;
}
case kArmI16x8LtS: {
__ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI16x8GtS: {
__ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI16x8LeS: {
__ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI16x8GeS: {
__ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI16x8UConvertI8x16Low: {
@ -1985,14 +1985,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kArmI16x8LtU: {
__ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI16x8GtU: {
__ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI16x8LeU: {
__ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI16x8GeU: {
__ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI8x16Splat: {
@ -2072,14 +2072,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vmvn(dst, dst);
break;
}
case kArmI8x16LtS: {
__ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI8x16GtS: {
__ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI8x16LeS: {
__ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI8x16GeS: {
__ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI8x16ShrU: {
@ -2110,14 +2110,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kArmI8x16LtU: {
__ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI8x16GtU: {
__ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI8x16LeU: {
__ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
case kArmI8x16GeU: {
__ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmS128Zero: {

24
src/compiler/arm/instruction-codes-arm.h
View File

@ -160,16 +160,16 @@ namespace compiler {
V(ArmI32x4MaxS) \
V(ArmI32x4Eq) \
V(ArmI32x4Ne) \
V(ArmI32x4LtS) \
V(ArmI32x4LeS) \
V(ArmI32x4GtS) \
V(ArmI32x4GeS) \
V(ArmI32x4UConvertF32x4) \
V(ArmI32x4UConvertI16x8Low) \
V(ArmI32x4UConvertI16x8High) \
V(ArmI32x4ShrU) \
V(ArmI32x4MinU) \
V(ArmI32x4MaxU) \
V(ArmI32x4LtU) \
V(ArmI32x4LeU) \
V(ArmI32x4GtU) \
V(ArmI32x4GeU) \
V(ArmI16x8Splat) \
V(ArmI16x8ExtractLane) \
V(ArmI16x8ReplaceLane) \
@ -189,8 +189,8 @@ namespace compiler {
V(ArmI16x8MaxS) \
V(ArmI16x8Eq) \
V(ArmI16x8Ne) \
V(ArmI16x8LtS) \
V(ArmI16x8LeS) \
V(ArmI16x8GtS) \
V(ArmI16x8GeS) \
V(ArmI16x8UConvertI8x16Low) \
V(ArmI16x8UConvertI8x16High) \
V(ArmI16x8ShrU) \
@ -199,8 +199,8 @@ namespace compiler {
V(ArmI16x8SubSaturateU) \
V(ArmI16x8MinU) \
V(ArmI16x8MaxU) \
V(ArmI16x8LtU) \
V(ArmI16x8LeU) \
V(ArmI16x8GtU) \
V(ArmI16x8GeU) \
V(ArmI8x16Splat) \
V(ArmI8x16ExtractLane) \
V(ArmI8x16ReplaceLane) \
@ -217,16 +217,16 @@ namespace compiler {
V(ArmI8x16MaxS) \
V(ArmI8x16Eq) \
V(ArmI8x16Ne) \
V(ArmI8x16LtS) \
V(ArmI8x16LeS) \
V(ArmI8x16GtS) \
V(ArmI8x16GeS) \
V(ArmI8x16ShrU) \
V(ArmI8x16UConvertI16x8) \
V(ArmI8x16AddSaturateU) \
V(ArmI8x16SubSaturateU) \
V(ArmI8x16MinU) \
V(ArmI8x16MaxU) \
V(ArmI8x16LtU) \
V(ArmI8x16LeU) \
V(ArmI8x16GtU) \
V(ArmI8x16GeU) \
V(ArmS128Zero) \
V(ArmS128And) \
V(ArmS128Or) \

24
src/compiler/arm/instruction-scheduler-arm.cc
View File

@ -144,16 +144,16 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI32x4MaxS:
case kArmI32x4Eq:
case kArmI32x4Ne:
case kArmI32x4LtS:
case kArmI32x4LeS:
case kArmI32x4GtS:
case kArmI32x4GeS:
case kArmI32x4UConvertF32x4:
case kArmI32x4UConvertI16x8Low:
case kArmI32x4UConvertI16x8High:
case kArmI32x4ShrU:
case kArmI32x4MinU:
case kArmI32x4MaxU:
case kArmI32x4LtU:
case kArmI32x4LeU:
case kArmI32x4GtU:
case kArmI32x4GeU:
case kArmI16x8Splat:
case kArmI16x8ExtractLane:
case kArmI16x8ReplaceLane:
@ -173,8 +173,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI16x8MaxS:
case kArmI16x8Eq:
case kArmI16x8Ne:
case kArmI16x8LtS:
case kArmI16x8LeS:
case kArmI16x8GtS:
case kArmI16x8GeS:
case kArmI16x8UConvertI8x16Low:
case kArmI16x8UConvertI8x16High:
case kArmI16x8ShrU:
@ -183,8 +183,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI16x8SubSaturateU:
case kArmI16x8MinU:
case kArmI16x8MaxU:
case kArmI16x8LtU:
case kArmI16x8LeU:
case kArmI16x8GtU:
case kArmI16x8GeU:
case kArmI8x16Splat:
case kArmI8x16ExtractLane:
case kArmI8x16ReplaceLane:
@ -201,16 +201,16 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmI8x16MaxS:
case kArmI8x16Eq:
case kArmI8x16Ne:
case kArmI8x16LtS:
case kArmI8x16LeS:
case kArmI8x16GtS:
case kArmI8x16GeS:
case kArmI8x16UConvertI16x8:
case kArmI8x16AddSaturateU:
case kArmI8x16SubSaturateU:
case kArmI8x16ShrU:
case kArmI8x16MinU:
case kArmI8x16MaxU:
case kArmI8x16LtU:
case kArmI8x16LeU:
case kArmI8x16GtU:
case kArmI8x16GeU:
case kArmS128Zero:
case kArmS128And:
case kArmS128Or:

24
src/compiler/arm/instruction-selector-arm.cc
View File

@ -2462,12 +2462,12 @@ VISIT_ATOMIC_BINOP(Xor)
V(I32x4MaxS, kArmI32x4MaxS) \
V(I32x4Eq, kArmI32x4Eq) \
V(I32x4Ne, kArmI32x4Ne) \
V(I32x4LtS, kArmI32x4LtS) \
V(I32x4LeS, kArmI32x4LeS) \
V(I32x4GtS, kArmI32x4GtS) \
V(I32x4GeS, kArmI32x4GeS) \
V(I32x4MinU, kArmI32x4MinU) \
V(I32x4MaxU, kArmI32x4MaxU) \
V(I32x4LtU, kArmI32x4LtU) \
V(I32x4LeU, kArmI32x4LeU) \
V(I32x4GtU, kArmI32x4GtU) \
V(I32x4GeU, kArmI32x4GeU) \
V(I16x8SConvertI32x4, kArmI16x8SConvertI32x4) \
V(I16x8Add, kArmI16x8Add) \
V(I16x8AddSaturateS, kArmI16x8AddSaturateS) \
@ -2479,15 +2479,15 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8MaxS, kArmI16x8MaxS) \
V(I16x8Eq, kArmI16x8Eq) \
V(I16x8Ne, kArmI16x8Ne) \
V(I16x8LtS, kArmI16x8LtS) \
V(I16x8LeS, kArmI16x8LeS) \
V(I16x8GtS, kArmI16x8GtS) \
V(I16x8GeS, kArmI16x8GeS) \
V(I16x8UConvertI32x4, kArmI16x8UConvertI32x4) \
V(I16x8AddSaturateU, kArmI16x8AddSaturateU) \
V(I16x8SubSaturateU, kArmI16x8SubSaturateU) \
V(I16x8MinU, kArmI16x8MinU) \
V(I16x8MaxU, kArmI16x8MaxU) \
V(I16x8LtU, kArmI16x8LtU) \
V(I16x8LeU, kArmI16x8LeU) \
V(I16x8GtU, kArmI16x8GtU) \
V(I16x8GeU, kArmI16x8GeU) \
V(I8x16SConvertI16x8, kArmI8x16SConvertI16x8) \
V(I8x16Add, kArmI8x16Add) \
V(I8x16AddSaturateS, kArmI8x16AddSaturateS) \
@ -2498,15 +2498,15 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16MaxS, kArmI8x16MaxS) \
V(I8x16Eq, kArmI8x16Eq) \
V(I8x16Ne, kArmI8x16Ne) \
V(I8x16LtS, kArmI8x16LtS) \
V(I8x16LeS, kArmI8x16LeS) \
V(I8x16GtS, kArmI8x16GtS) \
V(I8x16GeS, kArmI8x16GeS) \
V(I8x16UConvertI16x8, kArmI8x16UConvertI16x8) \
V(I8x16AddSaturateU, kArmI8x16AddSaturateU) \
V(I8x16SubSaturateU, kArmI8x16SubSaturateU) \
V(I8x16MinU, kArmI8x16MinU) \
V(I8x16MaxU, kArmI8x16MaxU) \
V(I8x16LtU, kArmI8x16LtU) \
V(I8x16LeU, kArmI8x16LeU) \
V(I8x16GtU, kArmI8x16GtU) \
V(I8x16GeU, kArmI8x16GeU) \
V(S128And, kArmS128And) \
V(S128Or, kArmS128Or) \
V(S128Xor, kArmS128Xor) \

72
src/compiler/instruction-selector.cc
View File

@ -1566,10 +1566,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x4(node), VisitI32x4Eq(node);
case IrOpcode::kI32x4Ne:
return MarkAsSimd1x4(node), VisitI32x4Ne(node);
case IrOpcode::kI32x4LtS:
return MarkAsSimd1x4(node), VisitI32x4LtS(node);
case IrOpcode::kI32x4LeS:
return MarkAsSimd1x4(node), VisitI32x4LeS(node);
case IrOpcode::kI32x4GtS:
return MarkAsSimd1x4(node), VisitI32x4GtS(node);
case IrOpcode::kI32x4GeS:
return MarkAsSimd1x4(node), VisitI32x4GeS(node);
case IrOpcode::kI32x4UConvertF32x4:
return MarkAsSimd128(node), VisitI32x4UConvertF32x4(node);
case IrOpcode::kI32x4UConvertI16x8Low:
@ -1582,10 +1582,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI32x4MinU(node);
case IrOpcode::kI32x4MaxU:
return MarkAsSimd128(node), VisitI32x4MaxU(node);
case IrOpcode::kI32x4LtU:
return MarkAsSimd1x4(node), VisitI32x4LtU(node);
case IrOpcode::kI32x4LeU:
return MarkAsSimd1x4(node), VisitI32x4LeU(node);
case IrOpcode::kI32x4GtU:
return MarkAsSimd1x4(node), VisitI32x4GtU(node);
case IrOpcode::kI32x4GeU:
return MarkAsSimd1x4(node), VisitI32x4GeU(node);
case IrOpcode::kI16x8Splat:
return MarkAsSimd128(node), VisitI16x8Splat(node);
case IrOpcode::kI16x8ExtractLane:
@ -1624,10 +1624,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x8(node), VisitI16x8Eq(node);
case IrOpcode::kI16x8Ne:
return MarkAsSimd1x8(node), VisitI16x8Ne(node);
case IrOpcode::kI16x8LtS:
return MarkAsSimd1x8(node), VisitI16x8LtS(node);
case IrOpcode::kI16x8LeS:
return MarkAsSimd1x8(node), VisitI16x8LeS(node);
case IrOpcode::kI16x8GtS:
return MarkAsSimd1x8(node), VisitI16x8GtS(node);
case IrOpcode::kI16x8GeS:
return MarkAsSimd1x8(node), VisitI16x8GeS(node);
case IrOpcode::kI16x8UConvertI8x16Low:
return MarkAsSimd128(node), VisitI16x8UConvertI8x16Low(node);
case IrOpcode::kI16x8UConvertI8x16High:
@ -1644,10 +1644,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI16x8MinU(node);
case IrOpcode::kI16x8MaxU:
return MarkAsSimd128(node), VisitI16x8MaxU(node);
case IrOpcode::kI16x8LtU:
return MarkAsSimd1x8(node), VisitI16x8LtU(node);
case IrOpcode::kI16x8LeU:
return MarkAsSimd1x8(node), VisitI16x8LeU(node);
case IrOpcode::kI16x8GtU:
return MarkAsSimd1x8(node), VisitI16x8GtU(node);
case IrOpcode::kI16x8GeU:
return MarkAsSimd1x8(node), VisitI16x8GeU(node);
case IrOpcode::kI8x16Splat:
return MarkAsSimd128(node), VisitI8x16Splat(node);
case IrOpcode::kI8x16ExtractLane:
@ -1680,10 +1680,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd1x16(node), VisitI8x16Eq(node);
case IrOpcode::kI8x16Ne:
return MarkAsSimd1x16(node), VisitI8x16Ne(node);
case IrOpcode::kI8x16LtS:
return MarkAsSimd1x16(node), VisitI8x16LtS(node);
case IrOpcode::kI8x16LeS:
return MarkAsSimd1x16(node), VisitI8x16LeS(node);
case IrOpcode::kI8x16GtS:
return MarkAsSimd1x16(node), VisitI8x16GtS(node);
case IrOpcode::kI8x16GeS:
return MarkAsSimd1x16(node), VisitI8x16GeS(node);
case IrOpcode::kI8x16ShrU:
return MarkAsSimd128(node), VisitI8x16ShrU(node);
case IrOpcode::kI8x16UConvertI16x8:
@ -1696,10 +1696,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI8x16MinU(node);
case IrOpcode::kI8x16MaxU:
return MarkAsSimd128(node), VisitI8x16MaxU(node);
case IrOpcode::kI8x16LtU:
return MarkAsSimd1x16(node), VisitI8x16LtU(node);
case IrOpcode::kI8x16LeU:
return MarkAsSimd1x16(node), VisitI16x8LeU(node);
case IrOpcode::kI8x16GtU:
return MarkAsSimd1x16(node), VisitI8x16GtU(node);
case IrOpcode::kI8x16GeU:
return MarkAsSimd1x16(node), VisitI16x8GeU(node);
case IrOpcode::kS128Zero:
return MarkAsSimd128(node), VisitS128Zero(node);
case IrOpcode::kS128And:
@ -2219,13 +2219,13 @@ void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4GeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4LeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4GeU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
@ -2305,13 +2305,13 @@ void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8LeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
@ -2363,9 +2363,9 @@ void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); }
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16LtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GtS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16LeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GeS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
@ -2389,9 +2389,9 @@ void InstructionSelector::VisitI8x16MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitI8x16LtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16LeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16GeU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM

24
src/compiler/machine-operator.cc
View File

@ -270,15 +270,15 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(I32x4MaxS, Operator::kCommutative, 2, 0, 1) \
V(I32x4Eq, Operator::kCommutative, 2, 0, 1) \
V(I32x4Ne, Operator::kCommutative, 2, 0, 1) \
V(I32x4LtS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4LeS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4GtS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4GeS, Operator::kNoProperties, 2, 0, 1) \
V(I32x4UConvertF32x4, Operator::kNoProperties, 1, 0, 1) \
V(I32x4UConvertI16x8Low, Operator::kNoProperties, 1, 0, 1) \
V(I32x4UConvertI16x8High, Operator::kNoProperties, 1, 0, 1) \
V(I32x4MinU, Operator::kCommutative, 2, 0, 1) \
V(I32x4MaxU, Operator::kCommutative, 2, 0, 1) \
V(I32x4LtU, Operator::kNoProperties, 2, 0, 1) \
V(I32x4LeU, Operator::kNoProperties, 2, 0, 1) \
V(I32x4GtU, Operator::kNoProperties, 2, 0, 1) \
V(I32x4GeU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8Splat, Operator::kNoProperties, 1, 0, 1) \
V(I16x8SConvertI8x16Low, Operator::kNoProperties, 1, 0, 1) \
V(I16x8SConvertI8x16High, Operator::kNoProperties, 1, 0, 1) \
@ -294,8 +294,8 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(I16x8MaxS, Operator::kCommutative, 2, 0, 1) \
V(I16x8Eq, Operator::kCommutative, 2, 0, 1) \
V(I16x8Ne, Operator::kCommutative, 2, 0, 1) \
V(I16x8LtS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8LeS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8GtS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8GeS, Operator::kNoProperties, 2, 0, 1) \
V(I16x8UConvertI8x16Low, Operator::kNoProperties, 1, 0, 1) \
V(I16x8UConvertI8x16High, Operator::kNoProperties, 1, 0, 1) \
V(I16x8UConvertI32x4, Operator::kNoProperties, 2, 0, 1) \
@ -303,8 +303,8 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(I16x8SubSaturateU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8MinU, Operator::kCommutative, 2, 0, 1) \
V(I16x8MaxU, Operator::kCommutative, 2, 0, 1) \
V(I16x8LtU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8LeU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8GtU, Operator::kNoProperties, 2, 0, 1) \
V(I16x8GeU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16Splat, Operator::kNoProperties, 1, 0, 1) \
V(I8x16Neg, Operator::kNoProperties, 1, 0, 1) \
V(I8x16SConvertI16x8, Operator::kNoProperties, 2, 0, 1) \
@ -317,15 +317,15 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(I8x16MaxS, Operator::kCommutative, 2, 0, 1) \
V(I8x16Eq, Operator::kCommutative, 2, 0, 1) \
V(I8x16Ne, Operator::kCommutative, 2, 0, 1) \
V(I8x16LtS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16LeS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16GtS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16GeS, Operator::kNoProperties, 2, 0, 1) \
V(I8x16UConvertI16x8, Operator::kNoProperties, 2, 0, 1) \
V(I8x16AddSaturateU, Operator::kCommutative, 2, 0, 1) \
V(I8x16SubSaturateU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16MinU, Operator::kCommutative, 2, 0, 1) \
V(I8x16MaxU, Operator::kCommutative, 2, 0, 1) \
V(I8x16LtU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16LeU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16GtU, Operator::kNoProperties, 2, 0, 1) \
V(I8x16GeU, Operator::kNoProperties, 2, 0, 1) \
V(S128Load, Operator::kNoProperties, 2, 0, 1) \
V(S128Store, Operator::kNoProperties, 3, 0, 1) \
V(S128Zero, Operator::kNoProperties, 0, 0, 1) \

24
src/compiler/machine-operator.h
View File

@ -494,8 +494,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I32x4MaxS();
const Operator* I32x4Eq();
const Operator* I32x4Ne();
const Operator* I32x4LtS();
const Operator* I32x4LeS();
const Operator* I32x4GtS();
const Operator* I32x4GeS();
const Operator* I32x4UConvertF32x4();
const Operator* I32x4UConvertI16x8Low();
@ -503,8 +503,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I32x4ShrU(int32_t);
const Operator* I32x4MinU();
const Operator* I32x4MaxU();
const Operator* I32x4LtU();
const Operator* I32x4LeU();
const Operator* I32x4GtU();
const Operator* I32x4GeU();
const Operator* I16x8Splat();
const Operator* I16x8ExtractLane(int32_t);
@ -525,8 +525,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I16x8MaxS();
const Operator* I16x8Eq();
const Operator* I16x8Ne();
const Operator* I16x8LtS();
const Operator* I16x8LeS();
const Operator* I16x8GtS();
const Operator* I16x8GeS();
const Operator* I16x8UConvertI8x16Low();
const Operator* I16x8UConvertI8x16High();
@ -536,8 +536,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I16x8SubSaturateU();
const Operator* I16x8MinU();
const Operator* I16x8MaxU();
const Operator* I16x8LtU();
const Operator* I16x8LeU();
const Operator* I16x8GtU();
const Operator* I16x8GeU();
const Operator* I8x16Splat();
const Operator* I8x16ExtractLane(int32_t);
@ -555,8 +555,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I8x16MaxS();
const Operator* I8x16Eq();
const Operator* I8x16Ne();
const Operator* I8x16LtS();
const Operator* I8x16LeS();
const Operator* I8x16GtS();
const Operator* I8x16GeS();
const Operator* I8x16ShrU(int32_t);
const Operator* I8x16UConvertI16x8();
@ -564,8 +564,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I8x16SubSaturateU();
const Operator* I8x16MinU();
const Operator* I8x16MaxU();
const Operator* I8x16LtU();
const Operator* I8x16LeU();
const Operator* I8x16GtU();
const Operator* I8x16GeU();
const Operator* S128Load();
const Operator* S128Store();

48
src/compiler/mips/code-generator-mips.cc
View File

@ -1885,28 +1885,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMipsI32x4LtS: {
case kMipsI32x4GtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI32x4LeS: {
case kMipsI32x4GeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI32x4LtU: {
case kMipsI32x4GtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI32x4LeU: {
case kMipsI32x4GeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI16x8Splat: {
@ -2010,16 +2010,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ nor_v(dst, dst, dst);
break;
}
case kMipsI16x8LtS: {
case kMipsI16x8GtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_s_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI16x8LeS: {
case kMipsI16x8GeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_s_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI16x8AddSaturateU: {
@ -2046,16 +2046,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsI16x8LtU: {
case kMipsI16x8GtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_u_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI16x8LeU: {
case kMipsI16x8GeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_u_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMipsI8x16Splat: {

16
src/compiler/mips/instruction-codes-mips.h
View File

@ -171,10 +171,10 @@ namespace compiler {
V(MipsI32x4SConvertF32x4) \
V(MipsI32x4UConvertF32x4) \
V(MipsI32x4Neg) \
V(MipsI32x4LtS) \
V(MipsI32x4LeS) \
V(MipsI32x4LtU) \
V(MipsI32x4LeU) \
V(MipsI32x4GtS) \
V(MipsI32x4GeS) \
V(MipsI32x4GtU) \
V(MipsI32x4GeU) \
V(MipsI16x8Splat) \
V(MipsI16x8ExtractLane) \
V(MipsI16x8ReplaceLane) \
@ -191,14 +191,14 @@ namespace compiler {
V(MipsI16x8MinS) \
V(MipsI16x8Eq) \
V(MipsI16x8Ne) \
V(MipsI16x8LtS) \
V(MipsI16x8LeS) \
V(MipsI16x8GtS) \
V(MipsI16x8GeS) \
V(MipsI16x8AddSaturateU) \
V(MipsI16x8SubSaturateU) \
V(MipsI16x8MaxU) \
V(MipsI16x8MinU) \
V(MipsI16x8LtU) \
V(MipsI16x8LeU) \
V(MipsI16x8GtU) \
V(MipsI16x8GeU) \
V(MipsI8x16Splat) \
V(MipsI8x16ExtractLane) \
V(MipsI8x16ReplaceLane) \

32
src/compiler/mips/instruction-selector-mips.cc
View File

@ -2109,20 +2109,20 @@ void InstructionSelector::VisitI32x4Neg(Node* node) {
VisitRR(this, kMipsI32x4Neg, node);
}
void InstructionSelector::VisitI32x4LtS(Node* node) {
VisitRRR(this, kMipsI32x4LtS, node);
void InstructionSelector::VisitI32x4GtS(Node* node) {
VisitRRR(this, kMipsI32x4GtS, node);
}
void InstructionSelector::VisitI32x4LeS(Node* node) {
VisitRRR(this, kMipsI32x4LeS, node);
void InstructionSelector::VisitI32x4GeS(Node* node) {
VisitRRR(this, kMipsI32x4GeS, node);
}
void InstructionSelector::VisitI32x4LtU(Node* node) {
VisitRRR(this, kMipsI32x4LtU, node);
void InstructionSelector::VisitI32x4GtU(Node* node) {
VisitRRR(this, kMipsI32x4GtU, node);
}
void InstructionSelector::VisitI32x4LeU(Node* node) {
VisitRRR(this, kMipsI32x4LeU, node);
void InstructionSelector::VisitI32x4GeU(Node* node) {
VisitRRR(this, kMipsI32x4GeU, node);
}
void InstructionSelector::VisitI16x8Splat(Node* node) {
@ -2189,12 +2189,12 @@ void InstructionSelector::VisitI16x8Ne(Node* node) {
VisitRRR(this, kMipsI16x8Ne, node);
}
void InstructionSelector::VisitI16x8LtS(Node* node) {
VisitRRR(this, kMipsI16x8LtS, node);
void InstructionSelector::VisitI16x8GtS(Node* node) {
VisitRRR(this, kMipsI16x8GtS, node);
}
void InstructionSelector::VisitI16x8LeS(Node* node) {
VisitRRR(this, kMipsI16x8LeS, node);
void InstructionSelector::VisitI16x8GeS(Node* node) {
VisitRRR(this, kMipsI16x8GeS, node);
}
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
@ -2213,12 +2213,12 @@ void InstructionSelector::VisitI16x8MinU(Node* node) {
VisitRRR(this, kMipsI16x8MinU, node);
}
void InstructionSelector::VisitI16x8LtU(Node* node) {
VisitRRR(this, kMipsI16x8LtU, node);
void InstructionSelector::VisitI16x8GtU(Node* node) {
VisitRRR(this, kMipsI16x8GtU, node);
}
void InstructionSelector::VisitI16x8LeU(Node* node) {
VisitRRR(this, kMipsI16x8LeU, node);
void InstructionSelector::VisitI16x8GeU(Node* node) {
VisitRRR(this, kMipsI16x8GeU, node);
}
void InstructionSelector::VisitI8x16Splat(Node* node) {

48
src/compiler/mips64/code-generator-mips64.cc
View File

@ -2206,28 +2206,28 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMips64I32x4LtS: {
case kMips64I32x4GtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_s_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I32x4LeS: {
case kMips64I32x4GeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_s_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I32x4LtU: {
case kMips64I32x4GtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_u_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I32x4LeU: {
case kMips64I32x4GeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_u_w(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I16x8Splat: {
@ -2331,16 +2331,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ nor_v(dst, dst, dst);
break;
}
case kMips64I16x8LtS: {
case kMips64I16x8GtS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_s_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I16x8LeS: {
case kMips64I16x8GeS: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_s_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I16x8AddSaturateU: {
@ -2367,16 +2367,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64I16x8LtU: {
case kMips64I16x8GtU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ clt_u_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ clt_u_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I16x8LeU: {
case kMips64I16x8GeU: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
__ cle_u_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ cle_u_h(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0));
break;
}
case kMips64I8x16Splat: {

16
src/compiler/mips64/instruction-codes-mips64.h
View File

@ -205,10 +205,10 @@ namespace compiler {
V(Mips64I32x4SConvertF32x4) \
V(Mips64I32x4UConvertF32x4) \
V(Mips64I32x4Neg) \
V(Mips64I32x4LtS) \
V(Mips64I32x4LeS) \
V(Mips64I32x4LtU) \
V(Mips64I32x4LeU) \
V(Mips64I32x4GtS) \
V(Mips64I32x4GeS) \
V(Mips64I32x4GtU) \
V(Mips64I32x4GeU) \
V(Mips64I16x8Splat) \
V(Mips64I16x8ExtractLane) \
V(Mips64I16x8ReplaceLane) \
@ -225,14 +225,14 @@ namespace compiler {
V(Mips64I16x8MinS) \
V(Mips64I16x8Eq) \
V(Mips64I16x8Ne) \
V(Mips64I16x8LtS) \
V(Mips64I16x8LeS) \
V(Mips64I16x8GtS) \
V(Mips64I16x8GeS) \
V(Mips64I16x8AddSaturateU) \
V(Mips64I16x8SubSaturateU) \
V(Mips64I16x8MaxU) \
V(Mips64I16x8MinU) \
V(Mips64I16x8LtU) \
V(Mips64I16x8LeU) \
V(Mips64I16x8GtU) \
V(Mips64I16x8GeU) \
V(Mips64I8x16Splat) \
V(Mips64I8x16ExtractLane) \
V(Mips64I8x16ReplaceLane) \

32
src/compiler/mips64/instruction-selector-mips64.cc
View File

@ -2861,20 +2861,20 @@ void InstructionSelector::VisitI32x4Neg(Node* node) {
VisitRR(this, kMips64I32x4Neg, node);
}
void InstructionSelector::VisitI32x4LtS(Node* node) {
VisitRRR(this, kMips64I32x4LtS, node);
void InstructionSelector::VisitI32x4GtS(Node* node) {
VisitRRR(this, kMips64I32x4GtS, node);
}
void InstructionSelector::VisitI32x4LeS(Node* node) {
VisitRRR(this, kMips64I32x4LeS, node);
void InstructionSelector::VisitI32x4GeS(Node* node) {
VisitRRR(this, kMips64I32x4GeS, node);
}
void InstructionSelector::VisitI32x4LtU(Node* node) {
VisitRRR(this, kMips64I32x4LtU, node);
void InstructionSelector::VisitI32x4GtU(Node* node) {
VisitRRR(this, kMips64I32x4GtU, node);
}
void InstructionSelector::VisitI32x4LeU(Node* node) {
VisitRRR(this, kMips64I32x4LeU, node);
void InstructionSelector::VisitI32x4GeU(Node* node) {
VisitRRR(this, kMips64I32x4GeU, node);
}
void InstructionSelector::VisitI16x8Splat(Node* node) {
@ -2941,12 +2941,12 @@ void InstructionSelector::VisitI16x8Ne(Node* node) {
VisitRRR(this, kMips64I16x8Ne, node);
}
void InstructionSelector::VisitI16x8LtS(Node* node) {
VisitRRR(this, kMips64I16x8LtS, node);
void InstructionSelector::VisitI16x8GtS(Node* node) {
VisitRRR(this, kMips64I16x8GtS, node);
}
void InstructionSelector::VisitI16x8LeS(Node* node) {
VisitRRR(this, kMips64I16x8LeS, node);
void InstructionSelector::VisitI16x8GeS(Node* node) {
VisitRRR(this, kMips64I16x8GeS, node);
}
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
@ -2965,12 +2965,12 @@ void InstructionSelector::VisitI16x8MinU(Node* node) {
VisitRRR(this, kMips64I16x8MinU, node);
}
void InstructionSelector::VisitI16x8LtU(Node* node) {
VisitRRR(this, kMips64I16x8LtU, node);
void InstructionSelector::VisitI16x8GtU(Node* node) {
VisitRRR(this, kMips64I16x8GtU, node);
}
void InstructionSelector::VisitI16x8LeU(Node* node) {
VisitRRR(this, kMips64I16x8LeU, node);
void InstructionSelector::VisitI16x8GeU(Node* node) {
VisitRRR(this, kMips64I16x8GeU, node);
}
void InstructionSelector::VisitI8x16Splat(Node* node) {

96
src/compiler/wasm-compiler.cc
View File

@ -3296,17 +3296,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I32x4Ne(), inputs[0],
inputs[1]);
case wasm::kExprI32x4LtS:
return graph()->NewNode(jsgraph()->machine()->I32x4LtS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I32x4GtS(), inputs[1],
inputs[0]);
case wasm::kExprI32x4LeS:
return graph()->NewNode(jsgraph()->machine()->I32x4LeS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I32x4GeS(), inputs[1],
inputs[0]);
case wasm::kExprI32x4GtS:
return graph()->NewNode(jsgraph()->machine()->I32x4LtS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I32x4GtS(), inputs[0],
inputs[1]);
case wasm::kExprI32x4GeS:
return graph()->NewNode(jsgraph()->machine()->I32x4LeS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I32x4GeS(), inputs[0],
inputs[1]);
case wasm::kExprI32x4UConvertI16x8Low:
return graph()->NewNode(jsgraph()->machine()->I32x4UConvertI16x8Low(),
inputs[0]);
@ -3320,17 +3320,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I32x4MaxU(), inputs[0],
inputs[1]);
case wasm::kExprI32x4LtU:
return graph()->NewNode(jsgraph()->machine()->I32x4LtU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I32x4GtU(), inputs[1],
inputs[0]);
case wasm::kExprI32x4LeU:
return graph()->NewNode(jsgraph()->machine()->I32x4LeU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I32x4GeU(), inputs[1],
inputs[0]);
case wasm::kExprI32x4GtU:
return graph()->NewNode(jsgraph()->machine()->I32x4LtU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I32x4GtU(), inputs[0],
inputs[1]);
case wasm::kExprI32x4GeU:
return graph()->NewNode(jsgraph()->machine()->I32x4LeU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I32x4GeU(), inputs[0],
inputs[1]);
case wasm::kExprI16x8Splat:
return graph()->NewNode(jsgraph()->machine()->I16x8Splat(), inputs[0]);
case wasm::kExprI16x8SConvertI8x16Low:
@ -3375,17 +3375,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I16x8Ne(), inputs[0],
inputs[1]);
case wasm::kExprI16x8LtS:
return graph()->NewNode(jsgraph()->machine()->I16x8LtS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I16x8GtS(), inputs[1],
inputs[0]);
case wasm::kExprI16x8LeS:
return graph()->NewNode(jsgraph()->machine()->I16x8LeS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I16x8GeS(), inputs[1],
inputs[0]);
case wasm::kExprI16x8GtS:
return graph()->NewNode(jsgraph()->machine()->I16x8LtS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I16x8GtS(), inputs[0],
inputs[1]);
case wasm::kExprI16x8GeS:
return graph()->NewNode(jsgraph()->machine()->I16x8LeS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I16x8GeS(), inputs[0],
inputs[1]);
case wasm::kExprI16x8UConvertI8x16Low:
return graph()->NewNode(jsgraph()->machine()->I16x8UConvertI8x16Low(),
inputs[0]);
@ -3408,17 +3408,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I16x8MaxU(), inputs[0],
inputs[1]);
case wasm::kExprI16x8LtU:
return graph()->NewNode(jsgraph()->machine()->I16x8LtU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I16x8GtU(), inputs[1],
inputs[0]);
case wasm::kExprI16x8LeU:
return graph()->NewNode(jsgraph()->machine()->I16x8LeU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I16x8GeU(), inputs[1],
inputs[0]);
case wasm::kExprI16x8GtU:
return graph()->NewNode(jsgraph()->machine()->I16x8LtU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I16x8GtU(), inputs[0],
inputs[1]);
case wasm::kExprI16x8GeU:
return graph()->NewNode(jsgraph()->machine()->I16x8LeU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I16x8GeU(), inputs[0],
inputs[1]);
case wasm::kExprI8x16Splat:
return graph()->NewNode(jsgraph()->machine()->I8x16Splat(), inputs[0]);
case wasm::kExprI8x16Neg:
@ -3454,17 +3454,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I8x16Ne(), inputs[0],
inputs[1]);
case wasm::kExprI8x16LtS:
return graph()->NewNode(jsgraph()->machine()->I8x16LtS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I8x16GtS(), inputs[1],
inputs[0]);
case wasm::kExprI8x16LeS:
return graph()->NewNode(jsgraph()->machine()->I8x16LeS(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I8x16GeS(), inputs[1],
inputs[0]);
case wasm::kExprI8x16GtS:
return graph()->NewNode(jsgraph()->machine()->I8x16LtS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I8x16GtS(), inputs[0],
inputs[1]);
case wasm::kExprI8x16GeS:
return graph()->NewNode(jsgraph()->machine()->I8x16LeS(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I8x16GeS(), inputs[0],
inputs[1]);
case wasm::kExprI8x16UConvertI16x8:
return graph()->NewNode(jsgraph()->machine()->I8x16UConvertI16x8(),
inputs[0], inputs[1]);
@ -3481,17 +3481,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
return graph()->NewNode(jsgraph()->machine()->I8x16MaxU(), inputs[0],
inputs[1]);
case wasm::kExprI8x16LtU:
return graph()->NewNode(jsgraph()->machine()->I8x16LtU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I8x16GtU(), inputs[1],
inputs[0]);
case wasm::kExprI8x16LeU:
return graph()->NewNode(jsgraph()->machine()->I8x16LeU(), inputs[0],
inputs[1]);
return graph()->NewNode(jsgraph()->machine()->I8x16GeU(), inputs[1],
inputs[0]);
case wasm::kExprI8x16GtU:
return graph()->NewNode(jsgraph()->machine()->I8x16LtU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I8x16GtU(), inputs[0],
inputs[1]);
case wasm::kExprI8x16GeU:
return graph()->NewNode(jsgraph()->machine()->I8x16LeU(), inputs[1],
inputs[0]);
return graph()->NewNode(jsgraph()->machine()->I8x16GeU(), inputs[0],
inputs[1]);
case wasm::kExprS128And:
return graph()->NewNode(jsgraph()->machine()->S128And(), inputs[0],
inputs[1]);

5
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -1506,7 +1506,10 @@ WASM_EXEC_COMPILED_TEST(I8x16Ne) {
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
WASM_EXEC_COMPILED_TEST(I8x16Mul) { RunI8x16BinOpTest(kExprI8x16Mul, Mul); }
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64
// TODO(gdeepti): Remove special case for ARM64 after v8:6421 is fixed
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET && !V8_TARGET_ARCH_ARM64
WASM_EXEC_COMPILED_TEST(I8x16GtS) {
RunI8x16CompareOpTest(kExprI8x16GtS, Greater);
}
@ -1538,7 +1541,7 @@ WASM_EXEC_COMPILED_TEST(I8x16LtU) {
WASM_EXEC_COMPILED_TEST(I8x16LeU) {
RunI8x16CompareOpTest(kExprI8x16LeU, UnsignedLessEqual);
}
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET
#endif // V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET && !V8_TARGET_ARCH_ARM64
void RunI8x16ShiftOpTest(WasmOpcode simd_op, Int8ShiftOp expected_op,
int shift) {