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[arm] Support CSDB instruction

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Add support for CSDB in the 32-bit assembler, disassembler and simulator.

Change-Id: I0e5432e4d219dd4699d5f9b7f911791acc87114c
Reviewed-on: https://chromium-review.googlesource.com/928522
Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Commit-Queue: Martyn Capewell <martyn.capewell@arm.com>
Cr-Commit-Position: refs/heads/master@{#51425}
This commit is contained in:
Martyn Capewell 2018-02-21 11:03:02 +00:00 committed by Commit Bot
parent 54640073f9
commit efb8508440
6 changed files with 30 additions and 6 deletions
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5
src/arm/assembler-arm.cc
View File

@ -2371,6 +2371,11 @@ void Assembler::isb(BarrierOption option) {
}
}
void Assembler::csdb() {
// Details available in Arm Cache Speculation Side-channels white paper,
// version 1.1, page 4.
emit(0xE320F014);
}
// Coprocessor instructions.
void Assembler::cdp(Coprocessor coproc,

3
src/arm/assembler-arm.h
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@ -960,6 +960,9 @@ class Assembler : public AssemblerBase {
void dsb(BarrierOption option);
void isb(BarrierOption option);
// Conditional speculation barrier.
void csdb();
// Coprocessor instructions
void cdp(Coprocessor coproc, int opcode_1,

4
src/arm/constants-arm.h
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@ -641,8 +641,8 @@ class Instruction {
&& (Bit(20) == 0)
&& ((Bit(7) == 0)); }
// Test for a nop instruction, which falls under type 1.
inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
// Test for nop-like instructions which fall under type 1.
inline bool IsNopLikeType1() const { return Bits(24, 8) == 0x120F0; }
// Test for a stop instruction.
inline bool IsStop() const {

10
src/arm/disasm-arm.cc
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@ -937,8 +937,14 @@ void Decoder::DecodeType01(Instruction* instr) {
} else {
Unknown(instr); // not used by V8
}
} else if ((type == 1) && instr->IsNopType1()) {
Format(instr, "nop'cond");
} else if ((type == 1) && instr->IsNopLikeType1()) {
if (instr->BitField(7, 0) == 0) {
Format(instr, "nop'cond");
} else if (instr->BitField(7, 0) == 20) {
Format(instr, "csdb");
} else {
Unknown(instr); // Not used in V8.
}
} else {
switch (instr->OpcodeField()) {
case AND: {

11
src/arm/simulator-arm.cc
View File

@ -2308,8 +2308,15 @@ void Simulator::DecodeType01(Instruction* instr) {
PrintF("%08x\n", instr->InstructionBits());
UNIMPLEMENTED();
}
} else if ((type == 1) && instr->IsNopType1()) {
// NOP.
} else if ((type == 1) && instr->IsNopLikeType1()) {
if (instr->BitField(7, 0) == 0) {
// NOP.
} else if (instr->BitField(7, 0) == 20) {
// CSDB.
} else {
PrintF("%08x\n", instr->InstructionBits());
UNIMPLEMENTED();
}
} else {
int rd = instr->RdValue();
int rn = instr->RnValue();

3
test/cctest/test-disasm-arm.cc
View File

@ -1568,6 +1568,9 @@ TEST(Barrier) {
COMPARE(mcr(p15, 0, r0, cr7, cr10, 4, ne), "1e070f9a mcrne (CP15DSB)");
COMPARE(mcr(p15, 0, r0, cr7, cr5, 4, mi), "4e070f95 mcrmi (CP15ISB)");
// Conditional speculation barrier.
COMPARE(csdb(), "e320f014 csdb");
VERIFY_RUN();
}