From efff3d18ec653e91b381809d8094addddef38243 Mon Sep 17 00:00:00 2001 From: Zhao Jiazhong Date: Mon, 2 Nov 2020 14:13:44 +0800 Subject: [PATCH] [mips64][wasm-simd] Implement v128.load32_zero v128.load64_zero Port 9124b7f97374bb1c6397889754ca14648e56e4d3 https://chromium-review.googlesource.com/c/v8/v8/+/2485250 Port f89869a213372ef3beb6ffb88c88795ee1a9a007 https://chromium-review.googlesource.com/c/v8/v8/+/2486236 Bug: v8:11038 Change-Id: Ia524e6ca11650b35916f1a78e7c859a570146a50 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2513870 Reviewed-by: Zhi An Ng Commit-Queue: Zhao Jiazhong Cr-Commit-Position: refs/heads/master@{#70937} --- .../backend/mips64/code-generator-mips64.cc | 16 ++++++++++++++++ .../backend/mips64/instruction-codes-mips64.h | 2 ++ .../mips64/instruction-scheduler-mips64.cc | 2 ++ .../mips64/instruction-selector-mips64.cc | 6 ++++++ .../baseline/mips64/liftoff-assembler-mips64.h | 10 ++++++++++ 5 files changed, 36 insertions(+) diff --git a/src/compiler/backend/mips64/code-generator-mips64.cc b/src/compiler/backend/mips64/code-generator-mips64.cc index c931d82a63..2091ae5e11 100644 --- a/src/compiler/backend/mips64/code-generator-mips64.cc +++ b/src/compiler/backend/mips64/code-generator-mips64.cc @@ -1949,6 +1949,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ ilvr_w(dst, kSimd128RegZero, dst); break; } + case kMips64S128Load32Zero: { + CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); + Simd128Register dst = i.OutputSimd128Register(); + __ xor_v(dst, dst, dst); + __ Lwu(kScratchReg, i.MemoryOperand()); + __ insert_w(dst, 0, kScratchReg); + break; + } + case kMips64S128Load64Zero: { + CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); + Simd128Register dst = i.OutputSimd128Register(); + __ xor_v(dst, dst, dst); + __ Ld(kScratchReg, i.MemoryOperand()); + __ insert_d(dst, 0, kScratchReg); + break; + } case kWord32AtomicLoadInt8: ASSEMBLE_ATOMIC_LOAD_INTEGER(Lb); break; diff --git a/src/compiler/backend/mips64/instruction-codes-mips64.h b/src/compiler/backend/mips64/instruction-codes-mips64.h index 10a974c827..18a8e616e7 100644 --- a/src/compiler/backend/mips64/instruction-codes-mips64.h +++ b/src/compiler/backend/mips64/instruction-codes-mips64.h @@ -359,6 +359,8 @@ namespace compiler { V(Mips64S128Load16x4U) \ V(Mips64S128Load32x2S) \ V(Mips64S128Load32x2U) \ + V(Mips64S128Load32Zero) \ + V(Mips64S128Load64Zero) \ V(Mips64MsaLd) \ V(Mips64MsaSt) \ V(Mips64I32x4SConvertI16x8Low) \ diff --git a/src/compiler/backend/mips64/instruction-scheduler-mips64.cc b/src/compiler/backend/mips64/instruction-scheduler-mips64.cc index bbab3c4b88..0cbaf0cc47 100644 --- a/src/compiler/backend/mips64/instruction-scheduler-mips64.cc +++ b/src/compiler/backend/mips64/instruction-scheduler-mips64.cc @@ -359,6 +359,8 @@ int InstructionScheduler::GetTargetInstructionFlags( case kMips64S128Load16x4U: case kMips64S128Load32x2S: case kMips64S128Load32x2U: + case kMips64S128Load32Zero: + case kMips64S128Load64Zero: case kMips64Word64AtomicLoadUint8: case kMips64Word64AtomicLoadUint16: case kMips64Word64AtomicLoadUint32: diff --git a/src/compiler/backend/mips64/instruction-selector-mips64.cc b/src/compiler/backend/mips64/instruction-selector-mips64.cc index 3d13506afc..216b83cdb2 100644 --- a/src/compiler/backend/mips64/instruction-selector-mips64.cc +++ b/src/compiler/backend/mips64/instruction-selector-mips64.cc @@ -416,6 +416,12 @@ void InstructionSelector::VisitLoadTransform(Node* node) { case LoadTransformation::kS128Load32x2U: opcode = kMips64S128Load32x2U; break; + case LoadTransformation::kS128Load32Zero: + opcode = kMips64S128Load32Zero; + break; + case LoadTransformation::kS128Load64Zero: + opcode = kMips64S128Load64Zero; + break; default: UNIMPLEMENTED(); } diff --git a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h index 83217722c8..59a50e7749 100644 --- a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h +++ b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h @@ -1509,6 +1509,16 @@ void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr, fill_d(dst_msa, scratch); ilvr_w(dst_msa, kSimd128RegZero, dst_msa); } + } else if (transform == LoadTransformationKind::kZeroExtend) { + xor_v(dst_msa, dst_msa, dst_msa); + if (memtype == MachineType::Int32()) { + Lwu(scratch, src_op); + insert_w(dst_msa, 0, scratch); + } else { + DCHECK_EQ(MachineType::Int64(), memtype); + Ld(scratch, src_op); + insert_d(dst_msa, 0, scratch); + } } else { DCHECK_EQ(LoadTransformationKind::kSplat, transform); if (memtype == MachineType::Int8()) {