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[ia32][wasm] Add F32x4 RecipApprox/RecipSqrtApprox.

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Add Rcpps and Rsqrtps macros.
Rename SIMD_UNOP macros.

Change-Id: I7e9418a835f085cc0fdd31fc3815c17c8f413b67
Reviewed-on: https://chromium-review.googlesource.com/982575
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Jing Bao <jing.bao@intel.com>
Cr-Commit-Position: refs/heads/master@{#52291}
This commit is contained in:
jing.bao 2018-03-28 12:38:22 +08:00 committed by Commit Bot
parent 54daf71954
commit f0f2234161
7 changed files with 31 additions and 25 deletions
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8
src/compiler/ia32/code-generator-ia32.cc
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@ -1846,6 +1846,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(0));
break;
}
case kIA32F32x4RecipApprox: {
__ Rcpps(i.OutputSimd128Register(), i.InputOperand(0));
break;
}
case kIA32F32x4RecipSqrtApprox: {
__ Rsqrtps(i.OutputSimd128Register(), i.InputOperand(0));
break;
}
case kSSEF32x4Add: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ addps(i.OutputSimd128Register(), i.InputOperand(1));

2
src/compiler/ia32/instruction-codes-ia32.h
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@ -128,6 +128,8 @@ namespace compiler {
V(AVXF32x4Abs) \
V(SSEF32x4Neg) \
V(AVXF32x4Neg) \
V(IA32F32x4RecipApprox) \
V(IA32F32x4RecipSqrtApprox) \
V(SSEF32x4Add) \
V(AVXF32x4Add) \
V(SSEF32x4Sub) \

2
src/compiler/ia32/instruction-scheduler-ia32.cc
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@ -110,6 +110,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXF32x4Abs:
case kSSEF32x4Neg:
case kAVXF32x4Neg:
case kIA32F32x4RecipApprox:
case kIA32F32x4RecipSqrtApprox:
case kSSEF32x4Add:
case kAVXF32x4Add:
case kSSEF32x4Sub:

32
src/compiler/ia32/instruction-selector-ia32.cc
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@ -1792,15 +1792,17 @@ VISIT_ATOMIC_BINOP(Xor)
V(S128Or) \
V(S128Xor)
#define SIMD_INT_UNOP_LIST(V) \
V(F32x4SConvertI32x4) \
V(I32x4Neg) \
V(I16x8Neg) \
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4) \
V(F32x4RecipApprox) \
V(F32x4RecipSqrtApprox) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg)
#define SIMD_OTHER_UNOP_LIST(V) \
V(F32x4Abs) \
V(F32x4Neg) \
#define SIMD_UNOP_PREFIX_LIST(V) \
V(F32x4Abs) \
V(F32x4Neg) \
V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \
@ -1943,24 +1945,24 @@ SIMD_SHIFT_OPCODES(VISIT_SIMD_SHIFT)
#undef VISIT_SIMD_SHIFT
#undef SIMD_SHIFT_OPCODES
#define VISIT_SIMD_INT_UNOP(Opcode) \
#define VISIT_SIMD_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
IA32OperandGenerator g(this); \
Emit(kIA32##Opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0))); \
}
SIMD_INT_UNOP_LIST(VISIT_SIMD_INT_UNOP)
#undef VISIT_SIMD_INT_UNOP
#undef SIMD_INT_UNOP_LIST
SIMD_UNOP_LIST(VISIT_SIMD_UNOP)
#undef VISIT_SIMD_UNOP
#undef SIMD_UNOP_LIST
#define VISIT_SIMD_OTHER_UNOP(Opcode) \
#define VISIT_SIMD_UNOP_PREFIX(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
IA32OperandGenerator g(this); \
InstructionCode opcode = IsSupported(AVX) ? kAVX##Opcode : kSSE##Opcode; \
Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0))); \
}
SIMD_OTHER_UNOP_LIST(VISIT_SIMD_OTHER_UNOP)
#undef VISIT_SIMD_OTHER_UNOP
#undef SIMD_OTHER_UNOP_LIST
SIMD_UNOP_PREFIX_LIST(VISIT_SIMD_UNOP_PREFIX)
#undef VISIT_SIMD_UNOP_PREFIX
#undef SIMD_UNOP_PREFIX_LIST
#define VISIT_SIMD_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \

6
src/compiler/instruction-selector.cc
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@ -2345,12 +2345,6 @@ void InstructionSelector::VisitWord64AtomicCompareExchange(Node* node) {
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_X64
void InstructionSelector::VisitF32x4RecipApprox(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitF32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64

2
src/ia32/macro-assembler-ia32.h
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@ -222,6 +222,8 @@ class TurboAssembler : public Assembler {
} \
}
AVX_OP2_WITH_TYPE(Rcpps, rcpps, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Rsqrtps, rsqrtps, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Movdqu, movdqu, XMMRegister, Operand)
AVX_OP2_WITH_TYPE(Movdqu, movdqu, Operand, XMMRegister)
AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register)

4
test/cctest/wasm/test-run-wasm-simd.cc
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@ -501,8 +501,6 @@ WASM_SIMD_TEST(F32x4Neg) {
RunF32x4UnOpTest(lower_simd, kExprF32x4Neg, Negate);
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_X64
static const float kApproxError = 0.01f;
WASM_SIMD_TEST(F32x4RecipApprox) {
@ -513,8 +511,6 @@ WASM_SIMD_TEST(F32x4RecipSqrtApprox) {
RunF32x4UnOpTest(lower_simd, kExprF32x4RecipSqrtApprox, RecipSqrt,
kApproxError);
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_X64
void RunF32x4BinOpTest(LowerSimd lower_simd, WasmOpcode simd_op,
FloatBinOp expected_op) {