Revert "[wasm-simd][arm] Prototype i8x16.popcnt"
This reverts commit e2aa734aef
.
Reason for revert: speculative revert for https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Mac64%20-%20debug/31901/blamelist
Original change's description:
> [wasm-simd][arm] Prototype i8x16.popcnt
>
> Bug: v8:11002
> Change-Id: Ib97e51ed52249a1af7a4b879396b70a016991719
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567534
> Commit-Queue: Zhi An Ng <zhin@chromium.org>
> Reviewed-by: Bill Budge <bbudge@chromium.org>
> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#71552}
TBR=bbudge@chromium.org,jkummerow@chromium.org,v8-arm-ports@googlegroups.com,zhin@chromium.org
Change-Id: Id1ae2dbaae52d45eb81ba8636178236ca8e9f7e0
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:11002
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2568925
Reviewed-by: Sathya Gunasekaran <gsathya@chromium.org>
Commit-Queue: Sathya Gunasekaran <gsathya@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71554}
This commit is contained in:
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@ -4799,7 +4799,7 @@ void Assembler::vext(QwNeonRegister dst, QwNeonRegister src1,
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n * B7 | B6 | m * B5 | vm);
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}
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enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN, VCNT };
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enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN };
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static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonRegType reg_type,
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NeonSize size, int dst_code, int src_code) {
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@ -4823,9 +4823,6 @@ static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonRegType reg_type,
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case VTRN:
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op_encoding = 0x2 * B16 | B7;
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break;
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case VCNT:
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op_encoding = 0xA * B7;
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break;
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default:
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UNREACHABLE();
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}
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@ -4910,13 +4907,6 @@ void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
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emit(EncodeNeonSizedOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
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}
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void Assembler::vcnt(QwNeonRegister dst, QwNeonRegister src) {
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// Qd = vcnt(Qm) SIMD Vector Count Set Bits.
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// Instruction details available at ARM DDI 0487F.b, F6-5094.
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DCHECK(IsEnabled(NEON));
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emit(EncodeNeonSizedOp(VCNT, NEON_Q, Neon8, dst.code(), src.code()));
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}
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// Encode NEON vtbl / vtbx instruction.
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static Instr EncodeNeonVTB(DwVfpRegister dst, const NeonListOperand& list,
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DwVfpRegister index, bool vtbx) {
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@ -966,8 +966,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void vtbx(DwVfpRegister dst, const NeonListOperand& list,
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DwVfpRegister index);
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void vcnt(QwNeonRegister dst, QwNeonRegister src);
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// Pseudo instructions
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// Different nop operations are used by the code generator to detect certain
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@ -1638,10 +1638,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputDoubleRegister(0));
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DCHECK_EQ(LeaveCC, i.OutputSBit());
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break;
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case kArmVcnt: {
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__ vcnt(i.OutputSimd128Register(), i.InputSimd128Register(0));
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break;
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}
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case kArmLdrb:
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__ ldrb(i.OutputRegister(), i.InputOffset());
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DCHECK_EQ(LeaveCC, i.OutputSBit());
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@ -110,7 +110,6 @@ namespace compiler {
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V(ArmVst1F64) \
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V(ArmVld1S128) \
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V(ArmVst1S128) \
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V(ArmVcnt) \
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V(ArmFloat32Max) \
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V(ArmFloat64Max) \
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V(ArmFloat32Min) \
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@ -103,7 +103,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kArmVmovHighF64U32:
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case kArmVmovF64U32U32:
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case kArmVmovU32U32F64:
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case kArmVcnt:
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case kArmFloat32Max:
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case kArmFloat64Max:
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case kArmFloat32Min:
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@ -2540,7 +2540,6 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
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V(I16x8Abs, kArmI16x8Abs) \
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V(I8x16Neg, kArmI8x16Neg) \
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V(I8x16Abs, kArmI8x16Abs) \
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V(I8x16Popcnt, kArmVcnt) \
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V(S128Not, kArmS128Not) \
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V(V32x4AnyTrue, kArmV32x4AnyTrue) \
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V(V32x4AllTrue, kArmV32x4AllTrue) \
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@ -2737,11 +2737,6 @@ void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
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#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X && !V8_TARGET_ARCH_ARM64
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// && !V8_TARGET_ARCH_IA32
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#if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM
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// TODO(v8:11002) Prototype i8x16.popcnt.
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void InstructionSelector::VisitI8x16Popcnt(Node* node) { UNIMPLEMENTED(); }
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#endif // !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_ARM
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#if !V8_TARGET_ARCH_ARM64
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// TODO(v8:10971) Prototype i16x8.q15mulr_sat_s
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void InstructionSelector::VisitI16x8Q15MulRSatS(Node* node) { UNIMPLEMENTED(); }
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@ -2763,6 +2758,9 @@ void InstructionSelector::VisitI64x2UConvertI32x4High(Node* node) {
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UNIMPLEMENTED();
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}
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// TODO(v8:11002) Prototype i8x16.popcnt.
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void InstructionSelector::VisitI8x16Popcnt(Node* node) { UNIMPLEMENTED(); }
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// TODO(v8:11008) Prototype extended multiplication.
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void InstructionSelector::VisitI64x2ExtMulLowI32x4S(Node* node) {
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UNIMPLEMENTED();
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@ -2268,9 +2268,6 @@ void Decoder::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
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"vrev%d.%d q%d, q%d", op, esize, Vd, Vm);
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} else if (size == 0 && opc1 == 0b10 && opc2 == 0) {
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Format(instr, q ? "vswp 'Qd, 'Qm" : "vswp 'Dd, 'Dm");
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} else if (opc1 == 0 && opc2 == 0b1010) {
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DCHECK_EQ(0, size);
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Format(instr, q ? "vcnt.8 'Qd, 'Qm" : "vcnt.8 'Dd, 'Dm");
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} else if (opc1 == 0 && opc2 == 0b1011) {
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Format(instr, "vmvn 'Qd, 'Qm");
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} else if (opc1 == 0b01 && (opc2 & 0b0111) == 0b110) {
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@ -4461,17 +4461,6 @@ void Simulator::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
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set_neon_register(vm, dval);
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set_neon_register(vd, mval);
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}
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} else if (opc1 == 0 && opc2 == 0b1010) {
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// vcnt Qd, Qm.
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DCHECK_EQ(0, size);
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int vd = instr->VFPDRegValue(q ? kSimd128Precision : kDoublePrecision);
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int vm = instr->VFPMRegValue(q ? kSimd128Precision : kDoublePrecision);
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uint8_t q_data[16];
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get_neon_register(vm, q_data);
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for (int i = 0; i < 16; i++) {
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q_data[i] = base::bits::CountPopulation(q_data[i]);
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}
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set_neon_register(vd, q_data);
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} else if (opc1 == 0 && opc2 == 0b1011) {
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// vmvn Qd, Qm.
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int vd = instr->VFPDRegValue(kSimd128Precision);
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@ -1323,8 +1323,6 @@ TEST(Neon) {
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"f3b1fa45 vtbx.8 d15, {d1, d2, d3}, d5");
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COMPARE(vtbx(d15, NeonListOperand(d1, 4), d5),
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"f3b1fb45 vtbx.8 d15, {d1, d2, d3, d4}, d5");
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COMPARE(vcnt(q1, q2),
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"f3b02544 vcnt.8 q1, q2");
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}
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VERIFY_RUN();
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@ -2545,7 +2545,7 @@ WASM_SIMD_TEST(I8x16Abs) {
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RunI8x16UnOpTest(execution_tier, lower_simd, kExprI8x16Abs, Abs);
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}
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#if V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
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#if V8_TARGET_ARCH_ARM64
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// TODO(v8:11002) Prototype i8x16.popcnt.
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WASM_SIMD_TEST_NO_LOWERING(I8x16Popcnt) {
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FLAG_SCOPE(wasm_simd_post_mvp);
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@ -2568,7 +2568,7 @@ WASM_SIMD_TEST_NO_LOWERING(I8x16Popcnt) {
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}
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}
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}
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#endif // V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_ARM
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#endif // V8_TARGET_ARCH_ARM64
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// Tests both signed and unsigned conversion from I16x8 (packing).
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WASM_SIMD_TEST(I8x16ConvertI16x8) {
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