diff --git a/src/compiler/backend/s390/code-generator-s390.cc b/src/compiler/backend/s390/code-generator-s390.cc index 8153d2a180..ff129d5e3b 100644 --- a/src/compiler/backend/s390/code-generator-s390.cc +++ b/src/compiler/backend/s390/code-generator-s390.cc @@ -3544,6 +3544,71 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } #undef CONVERT_INT32_TO_FLOAT +#define VECTOR_UNPACK(op, mode) \ + __ op(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0), \ + Condition(0), Condition(mode)); + case kS390_I32x4SConvertI16x8Low: { + VECTOR_UNPACK(vupl, 1); + break; + } + case kS390_I32x4SConvertI16x8High: { + VECTOR_UNPACK(vuph, 1); + break; + } + case kS390_I32x4UConvertI16x8Low: { + VECTOR_UNPACK(vupll, 1); + break; + } + case kS390_I32x4UConvertI16x8High: { + VECTOR_UNPACK(vuplh, 1); + break; + } + case kS390_I16x8SConvertI8x16Low: { + VECTOR_UNPACK(vupl, 0); + break; + } + case kS390_I16x8SConvertI8x16High: { + VECTOR_UNPACK(vuph, 0); + break; + } + case kS390_I16x8UConvertI8x16Low: { + VECTOR_UNPACK(vupll, 0); + break; + } + case kS390_I16x8UConvertI8x16High: { + VECTOR_UNPACK(vuplh, 0); + break; + } +#undef VECTOR_UNPACK + case kS390_I16x8SConvertI32x4: + __ vpks(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1), Condition(0), Condition(2)); + break; + case kS390_I8x16SConvertI16x8: + __ vpks(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1), Condition(0), Condition(1)); + break; +#define VECTOR_PACK_UNSIGNED(mode) \ + Simd128Register tempFPReg = i.ToSimd128Register(instr->TempAt(0)); \ + __ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, Condition(0), \ + Condition(0), Condition(mode)); \ + __ vmx(tempFPReg, i.InputSimd128Register(0), kScratchDoubleReg, \ + Condition(0), Condition(0), Condition(mode)); \ + __ vmx(kScratchDoubleReg, i.InputSimd128Register(1), kScratchDoubleReg, \ + Condition(0), Condition(0), Condition(mode)); \ + __ vpkls(i.OutputSimd128Register(), tempFPReg, kScratchDoubleReg, \ + Condition(0), Condition(mode)); + case kS390_I16x8UConvertI32x4: { + // treat inputs as signed, and saturate to unsigned (negative to 0) + VECTOR_PACK_UNSIGNED(2) + break; + } + case kS390_I8x16UConvertI16x8: { + // treat inputs as signed, and saturate to unsigned (negative to 0) + VECTOR_PACK_UNSIGNED(1) + break; + } +#undef VECTOR_PACK_UNSIGNED default: UNREACHABLE(); } diff --git a/src/compiler/backend/s390/instruction-codes-s390.h b/src/compiler/backend/s390/instruction-codes-s390.h index 96369bcdb6..30d9b430a8 100644 --- a/src/compiler/backend/s390/instruction-codes-s390.h +++ b/src/compiler/backend/s390/instruction-codes-s390.h @@ -212,6 +212,8 @@ namespace compiler { V(S390_F32x4Neg) \ V(S390_F32x4RecipApprox) \ V(S390_F32x4RecipSqrtApprox) \ + V(S390_F32x4SConvertI32x4) \ + V(S390_F32x4UConvertI32x4) \ V(S390_I32x4Splat) \ V(S390_I32x4ExtractLane) \ V(S390_I32x4ReplaceLane) \ @@ -236,8 +238,10 @@ namespace compiler { V(S390_I32x4ShrU) \ V(S390_I32x4SConvertF32x4) \ V(S390_I32x4UConvertF32x4) \ - V(S390_F32x4SConvertI32x4) \ - V(S390_F32x4UConvertI32x4) \ + V(S390_I32x4SConvertI16x8Low) \ + V(S390_I32x4SConvertI16x8High) \ + V(S390_I32x4UConvertI16x8Low) \ + V(S390_I32x4UConvertI16x8High) \ V(S390_I16x8ExtractLaneU) \ V(S390_I16x8ExtractLaneS) \ V(S390_I16x8ReplaceLane) \ @@ -259,6 +263,12 @@ namespace compiler { V(S390_I16x8ShrS) \ V(S390_I16x8ShrU) \ V(S390_I16x8Neg) \ + V(S390_I16x8SConvertI32x4) \ + V(S390_I16x8UConvertI32x4) \ + V(S390_I16x8SConvertI8x16Low) \ + V(S390_I16x8SConvertI8x16High) \ + V(S390_I16x8UConvertI8x16Low) \ + V(S390_I16x8UConvertI8x16High) \ V(S390_I8x16Splat) \ V(S390_I8x16ExtractLaneU) \ V(S390_I8x16ExtractLaneS) \ @@ -280,6 +290,8 @@ namespace compiler { V(S390_I8x16ShrS) \ V(S390_I8x16ShrU) \ V(S390_I8x16Neg) \ + V(S390_I8x16SConvertI16x8) \ + V(S390_I8x16UConvertI16x8) \ V(S390_S1x4AnyTrue) \ V(S390_S1x8AnyTrue) \ V(S390_S1x16AnyTrue) \ diff --git a/src/compiler/backend/s390/instruction-scheduler-s390.cc b/src/compiler/backend/s390/instruction-scheduler-s390.cc index 27b7ffedb5..f222adb101 100644 --- a/src/compiler/backend/s390/instruction-scheduler-s390.cc +++ b/src/compiler/backend/s390/instruction-scheduler-s390.cc @@ -158,6 +158,8 @@ int InstructionScheduler::GetTargetInstructionFlags( case kS390_F32x4Neg: case kS390_F32x4RecipApprox: case kS390_F32x4RecipSqrtApprox: + case kS390_F32x4SConvertI32x4: + case kS390_F32x4UConvertI32x4: case kS390_I32x4Splat: case kS390_I32x4ExtractLane: case kS390_I32x4ReplaceLane: @@ -181,8 +183,10 @@ int InstructionScheduler::GetTargetInstructionFlags( case kS390_I32x4Neg: case kS390_I32x4SConvertF32x4: case kS390_I32x4UConvertF32x4: - case kS390_F32x4SConvertI32x4: - case kS390_F32x4UConvertI32x4: + case kS390_I32x4SConvertI16x8Low: + case kS390_I32x4SConvertI16x8High: + case kS390_I32x4UConvertI16x8Low: + case kS390_I32x4UConvertI16x8High: case kS390_I16x8Splat: case kS390_I16x8ExtractLaneU: case kS390_I16x8ExtractLaneS: @@ -205,6 +209,12 @@ int InstructionScheduler::GetTargetInstructionFlags( case kS390_I16x8ShrS: case kS390_I16x8ShrU: case kS390_I16x8Neg: + case kS390_I16x8SConvertI32x4: + case kS390_I16x8UConvertI32x4: + case kS390_I16x8SConvertI8x16Low: + case kS390_I16x8SConvertI8x16High: + case kS390_I16x8UConvertI8x16Low: + case kS390_I16x8UConvertI8x16High: case kS390_I8x16Splat: case kS390_I8x16ExtractLaneU: case kS390_I8x16ExtractLaneS: @@ -226,6 +236,8 @@ int InstructionScheduler::GetTargetInstructionFlags( case kS390_I8x16ShrS: case kS390_I8x16ShrU: case kS390_I8x16Neg: + case kS390_I8x16SConvertI16x8: + case kS390_I8x16UConvertI16x8: case kS390_S1x4AnyTrue: case kS390_S1x8AnyTrue: case kS390_S1x16AnyTrue: diff --git a/src/compiler/backend/s390/instruction-selector-s390.cc b/src/compiler/backend/s390/instruction-selector-s390.cc index ded7adf40a..e6f2bcc848 100644 --- a/src/compiler/backend/s390/instruction-selector-s390.cc +++ b/src/compiler/backend/s390/instruction-selector-s390.cc @@ -2554,6 +2554,8 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { V(I16x8GeS) \ V(I16x8GtU) \ V(I16x8GeU) \ + V(I16x8SConvertI32x4) \ + V(I16x8UConvertI32x4) \ V(I8x16Add) \ V(I8x16Sub) \ V(I8x16Mul) \ @@ -2567,18 +2569,28 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) { V(I8x16GeS) \ V(I8x16GtU) \ V(I8x16GeU) \ + V(I8x16SConvertI16x8) \ + V(I8x16UConvertI16x8) \ V(S128And) \ V(S128Or) \ V(S128Xor) -#define SIMD_UNOP_LIST(V) \ - V(F32x4Abs) \ - V(F32x4Neg) \ - V(F32x4RecipApprox) \ - V(F32x4RecipSqrtApprox) \ - V(I32x4Neg) \ - V(I16x8Neg) \ - V(I8x16Neg) \ +#define SIMD_UNOP_LIST(V) \ + V(F32x4Abs) \ + V(F32x4Neg) \ + V(F32x4RecipApprox) \ + V(F32x4RecipSqrtApprox) \ + V(I32x4Neg) \ + V(I32x4SConvertI16x8Low) \ + V(I32x4SConvertI16x8High) \ + V(I32x4UConvertI16x8Low) \ + V(I32x4UConvertI16x8High) \ + V(I16x8Neg) \ + V(I16x8SConvertI8x16Low) \ + V(I16x8SConvertI8x16High) \ + V(I16x8UConvertI8x16Low) \ + V(I16x8UConvertI8x16High) \ + V(I8x16Neg) \ V(S128Not) #define SIMD_SHIFT_LIST(V) \ @@ -2783,53 +2795,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI16x8UConvertI8x16Low(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) { - UNIMPLEMENTED(); -} -void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) { - UNIMPLEMENTED(); -} - -void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) { - UNIMPLEMENTED(); -} - void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }