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Use fast_sqrt instead of std::sqrt in simulators.

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This prevents clang from inlining and returning inconsistent results.

R=bmeurer@chromium.org
BUG=v8:3802
LOG=N

Review URL: https://codereview.chromium.org/831393006

Cr-Commit-Position: refs/heads/master@{#26158}
This commit is contained in:
yangguo 2015-01-20 05:53:34 -08:00 committed by Commit bot
parent e99faf93ff
commit f38e48be60
5 changed files with 8 additions and 5 deletions
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2
src/arm/simulator-arm.cc
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@ -3069,7 +3069,7 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
} else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
// vsqrt
double dm_value = get_double_from_d_register(vm);
double dd_value = std::sqrt(dm_value);
double dd_value = fast_sqrt(dm_value);
dd_value = canonicalizeNaN(dd_value);
set_d_register_from_double(vd, dd_value);
} else if (instr->Opc3Value() == 0x0) {

3
src/arm64/simulator-arm64.cc
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@ -12,6 +12,7 @@
#include "src/arm64/decoder-arm64-inl.h"
#include "src/arm64/simulator-arm64.h"
#include "src/assembler.h"
#include "src/codegen.h"
#include "src/disasm.h"
#include "src/macro-assembler.h"
#include "src/ostreams.h"
@ -3100,7 +3101,7 @@ T Simulator::FPSqrt(T op) {
} else if (op < 0.0) {
return FPDefaultNaN<T>();
} else {
return std::sqrt(op);
return fast_sqrt(op);
}
}

3
src/mips/simulator-mips.cc
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@ -13,6 +13,7 @@
#include "src/assembler.h"
#include "src/base/bits.h"
#include "src/codegen.h"
#include "src/disasm.h"
#include "src/mips/constants-mips.h"
#include "src/mips/simulator-mips.h"
@ -2244,7 +2245,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
set_fpu_register_double(fd_reg, -fs);
break;
case SQRT_D:
set_fpu_register_double(fd_reg, sqrt(fs));
set_fpu_register_double(fd_reg, fast_sqrt(fs));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));

3
src/mips64/simulator-mips64.cc
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@ -13,6 +13,7 @@
#include "src/assembler.h"
#include "src/base/bits.h"
#include "src/codegen.h"
#include "src/disasm.h"
#include "src/mips64/constants-mips64.h"
#include "src/mips64/simulator-mips64.h"
@ -2391,7 +2392,7 @@ void Simulator::DecodeTypeRegister(Instruction* instr) {
set_fpu_register_double(fd_reg, -fs);
break;
case SQRT_D:
set_fpu_register_double(fd_reg, sqrt(fs));
set_fpu_register_double(fd_reg, fast_sqrt(fs));
break;
case C_UN_D:
set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));

2
src/ppc/simulator-ppc.cc
View File

@ -2613,7 +2613,7 @@ void Simulator::ExecuteExt4(Instruction* instr) {
int frt = instr->RTValue();
int frb = instr->RBValue();
double frb_val = get_double_from_d_register(frb);
double frt_val = std::sqrt(frb_val);
double frt_val = fast_sqrt(frb_val);
set_d_register_from_double(frt, frt_val);
return;
}