From f3ad100a117a870fb569709088ff0812643e8c4c Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 18 Nov 2021 09:39:20 -0800 Subject: [PATCH] [wasm-relaxed-simd][arm64] Implement relaxed trunc Bug: v8:12284 Change-Id: Ia5dd40ffd1854ed8f1d6138a1bf40d8f2ca79793 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3272642 Reviewed-by: Deepti Gandluri Commit-Queue: Zhi An Ng Cr-Commit-Position: refs/heads/main@{#78025} --- .../arm64/instruction-selector-arm64.cc | 48 ++++++++++--------- src/compiler/backend/instruction-selector.cc | 5 +- .../cctest/wasm/test-run-wasm-relaxed-simd.cc | 4 +- 3 files changed, 29 insertions(+), 28 deletions(-) diff --git a/src/compiler/backend/arm64/instruction-selector-arm64.cc b/src/compiler/backend/arm64/instruction-selector-arm64.cc index 4c9a0eb92c..ad32aee12b 100644 --- a/src/compiler/backend/arm64/instruction-selector-arm64.cc +++ b/src/compiler/backend/arm64/instruction-selector-arm64.cc @@ -3474,28 +3474,32 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { UNREACHABLE(); } -#define SIMD_UNOP_LIST(V) \ - V(F64x2ConvertLowI32x4S, kArm64F64x2ConvertLowI32x4S) \ - V(F64x2ConvertLowI32x4U, kArm64F64x2ConvertLowI32x4U) \ - V(F64x2PromoteLowF32x4, kArm64F64x2PromoteLowF32x4) \ - V(F32x4SConvertI32x4, kArm64F32x4SConvertI32x4) \ - V(F32x4UConvertI32x4, kArm64F32x4UConvertI32x4) \ - V(F32x4RecipApprox, kArm64F32x4RecipApprox) \ - V(F32x4RecipSqrtApprox, kArm64F32x4RecipSqrtApprox) \ - V(F32x4DemoteF64x2Zero, kArm64F32x4DemoteF64x2Zero) \ - V(I64x2BitMask, kArm64I64x2BitMask) \ - V(I32x4SConvertF32x4, kArm64I32x4SConvertF32x4) \ - V(I32x4UConvertF32x4, kArm64I32x4UConvertF32x4) \ - V(I32x4BitMask, kArm64I32x4BitMask) \ - V(I32x4TruncSatF64x2SZero, kArm64I32x4TruncSatF64x2SZero) \ - V(I32x4TruncSatF64x2UZero, kArm64I32x4TruncSatF64x2UZero) \ - V(I16x8BitMask, kArm64I16x8BitMask) \ - V(I8x16BitMask, kArm64I8x16BitMask) \ - V(S128Not, kArm64S128Not) \ - V(V128AnyTrue, kArm64V128AnyTrue) \ - V(I64x2AllTrue, kArm64I64x2AllTrue) \ - V(I32x4AllTrue, kArm64I32x4AllTrue) \ - V(I16x8AllTrue, kArm64I16x8AllTrue) \ +#define SIMD_UNOP_LIST(V) \ + V(F64x2ConvertLowI32x4S, kArm64F64x2ConvertLowI32x4S) \ + V(F64x2ConvertLowI32x4U, kArm64F64x2ConvertLowI32x4U) \ + V(F64x2PromoteLowF32x4, kArm64F64x2PromoteLowF32x4) \ + V(F32x4SConvertI32x4, kArm64F32x4SConvertI32x4) \ + V(F32x4UConvertI32x4, kArm64F32x4UConvertI32x4) \ + V(F32x4RecipApprox, kArm64F32x4RecipApprox) \ + V(F32x4RecipSqrtApprox, kArm64F32x4RecipSqrtApprox) \ + V(F32x4DemoteF64x2Zero, kArm64F32x4DemoteF64x2Zero) \ + V(I64x2BitMask, kArm64I64x2BitMask) \ + V(I32x4SConvertF32x4, kArm64I32x4SConvertF32x4) \ + V(I32x4UConvertF32x4, kArm64I32x4UConvertF32x4) \ + V(I32x4RelaxedTruncF32x4S, kArm64I32x4SConvertF32x4) \ + V(I32x4RelaxedTruncF32x4U, kArm64I32x4UConvertF32x4) \ + V(I32x4BitMask, kArm64I32x4BitMask) \ + V(I32x4TruncSatF64x2SZero, kArm64I32x4TruncSatF64x2SZero) \ + V(I32x4TruncSatF64x2UZero, kArm64I32x4TruncSatF64x2UZero) \ + V(I32x4RelaxedTruncF64x2SZero, kArm64I32x4TruncSatF64x2SZero) \ + V(I32x4RelaxedTruncF64x2UZero, kArm64I32x4TruncSatF64x2UZero) \ + V(I16x8BitMask, kArm64I16x8BitMask) \ + V(I8x16BitMask, kArm64I8x16BitMask) \ + V(S128Not, kArm64S128Not) \ + V(V128AnyTrue, kArm64V128AnyTrue) \ + V(I64x2AllTrue, kArm64I64x2AllTrue) \ + V(I32x4AllTrue, kArm64I32x4AllTrue) \ + V(I16x8AllTrue, kArm64I16x8AllTrue) \ V(I8x16AllTrue, kArm64I8x16AllTrue) #define SIMD_UNOP_LANE_SIZE_LIST(V) \ diff --git a/src/compiler/backend/instruction-selector.cc b/src/compiler/backend/instruction-selector.cc index 1fb5657bf1..fc04b37ec3 100644 --- a/src/compiler/backend/instruction-selector.cc +++ b/src/compiler/backend/instruction-selector.cc @@ -2811,9 +2811,6 @@ void InstructionSelector::VisitF32x4RelaxedMin(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF32x4RelaxedMax(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2RelaxedMin(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitF64x2RelaxedMax(Node* node) { UNIMPLEMENTED(); } -#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 - -#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 void InstructionSelector::VisitI32x4RelaxedTruncF64x2SZero(Node* node) { UNIMPLEMENTED(); } @@ -2826,7 +2823,7 @@ void InstructionSelector::VisitI32x4RelaxedTruncF32x4S(Node* node) { void InstructionSelector::VisitI32x4RelaxedTruncF32x4U(Node* node) { UNIMPLEMENTED(); } -#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 +#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); } diff --git a/test/cctest/wasm/test-run-wasm-relaxed-simd.cc b/test/cctest/wasm/test-run-wasm-relaxed-simd.cc index 2f6d9e69c9..bb1205f3ce 100644 --- a/test/cctest/wasm/test-run-wasm-relaxed-simd.cc +++ b/test/cctest/wasm/test-run-wasm-relaxed-simd.cc @@ -329,9 +329,7 @@ WASM_RELAXED_SIMD_TEST(F64x2RelaxedMin) { WASM_RELAXED_SIMD_TEST(F64x2RelaxedMax) { RunF64x2BinOpTest(execution_tier, kExprF64x2RelaxedMax, Maximum); } -#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM64 -#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 namespace { // For relaxed trunc instructions, don't test out of range values. // FloatType comes later so caller can rely on template argument deduction and @@ -387,7 +385,9 @@ WASM_RELAXED_SIMD_TEST(I32x4RelaxedTruncF32x4U) { IntRelaxedTruncFloatTest( execution_tier, kExprI32x4RelaxedTruncF32x4U, kExprF32x4Splat); } +#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM64 +#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 WASM_RELAXED_SIMD_TEST(I8x16RelaxedSwizzle) { // Output is only defined for indices in the range [0,15]. WasmRunner r(execution_tier);