Fix the ARM simulator's stop support and add conditional breakpoint.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6346009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6405 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
ager@chromium.org 2011-01-19 15:39:40 +00:00
parent 70910af7a0
commit f6e177f075
3 changed files with 18 additions and 3 deletions

View File

@ -1656,8 +1656,14 @@ void Assembler::stop(const char* msg, Condition cond, int32_t code) {
emit(reinterpret_cast<Instr>(msg));
#else // def __arm__
#ifdef CAN_USE_ARMV5_INSTRUCTIONS
ASSERT(cond == al);
bkpt(0);
if (cond != al) {
Label skip;
b(&skip, NegateCondition(cond));
bkpt(0);
bind(&skip);
} else {
bkpt(0);
}
#else // ndef CAN_USE_ARMV5_INSTRUCTIONS
svc(0x9f0001, cond);
#endif // ndef CAN_USE_ARMV5_INSTRUCTIONS

View File

@ -352,6 +352,11 @@ class Instr {
&& (Bit(20) == 0)
&& ((Bit(7) == 0)); }
// Test for a stop instruction.
inline bool IsStop() const {
return (TypeField() == 7) && (Bit(24) == 1) && (SvcField() >= stop);
}
// Special accessors that test for existence of a value.
inline bool HasS() const { return SField() == 1; }
inline bool HasB() const { return BField() == 1; }

View File

@ -455,7 +455,7 @@ void Debugger::Debug() {
PrintF("DIV BY ZERO flag: %d; ", sim_->div_zero_vfp_flag_);
PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_);
PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_);
PrintF("INEXACT flag: %d; ", sim_->inexact_vfp_flag_);
PrintF("INEXACT flag: %d;\n", sim_->inexact_vfp_flag_);
} else if (strcmp(cmd, "stop") == 0) {
int32_t value;
intptr_t stop_pc = sim_->get_pc() - 2 * Instr::kInstrSize;
@ -2907,6 +2907,10 @@ void Simulator::InstructionDecode(Instr* instr) {
break;
}
}
// If the instruction is a non taken conditional stop, we need to skip the
// inlined message address.
} else if (instr->IsStop()) {
set_pc(get_pc() + 2 * Instr::kInstrSize);
}
if (!pc_modified_) {
set_register(pc, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize);