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PPC: Implement turbofan Float64Min and Float64Max machine operators.

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R=danno@chromium.org, svenpanne@chromium.org

BUG=

Review URL: https://codereview.chromium.org/1006913002

Cr-Commit-Position: refs/heads/master@{#27202}
This commit is contained in:
michael_dawson 2015-03-16 01:01:51 -07:00 committed by Commit bot
parent 523dec1234
commit f9cceb90f1
3 changed files with 33 additions and 3 deletions
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22
src/compiler/ppc/code-generator-ppc.cc
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@ -339,6 +339,22 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
} while (0)
#define ASSEMBLE_FLOAT_MAX(scratch_reg) \
do { \
__ fsub(scratch_reg, i.InputDoubleRegister(0), i.InputDoubleRegister(1)); \
__ fsel(i.OutputDoubleRegister(), scratch_reg, i.InputDoubleRegister(0), \
i.InputDoubleRegister(1)); \
} while (0)
#define ASSEMBLE_FLOAT_MIN(scratch_reg) \
do { \
__ fsub(scratch_reg, i.InputDoubleRegister(0), i.InputDoubleRegister(1)); \
__ fsel(i.OutputDoubleRegister(), scratch_reg, i.InputDoubleRegister(1), \
i.InputDoubleRegister(0)); \
} while (0)
#define ASSEMBLE_LOAD_FLOAT(asm_instr, asm_instrx) \
do { \
DoubleRegister result = i.OutputDoubleRegister(); \
@ -799,6 +815,12 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
case kPPC_Neg64:
__ neg(i.OutputRegister(), i.InputRegister(0), LeaveOE, i.OutputRCBit());
break;
case kPPC_MaxFloat64:
ASSEMBLE_FLOAT_MAX(kScratchDoubleReg);
break;
case kPPC_MinFloat64:
ASSEMBLE_FLOAT_MIN(kScratchDoubleReg);
break;
case kPPC_SqrtFloat64:
ASSEMBLE_FLOAT_UNOP_RC(fsqrt);
break;

2
src/compiler/ppc/instruction-codes-ppc.h
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@ -67,6 +67,8 @@ namespace compiler {
V(PPC_CeilFloat64) \
V(PPC_TruncateFloat64) \
V(PPC_RoundFloat64) \
V(PPC_MaxFloat64) \
V(PPC_MinFloat64) \
V(PPC_Cmp32) \
V(PPC_Cmp64) \
V(PPC_CmpFloat64) \

12
src/compiler/ppc/instruction-selector-ppc.cc
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@ -963,10 +963,14 @@ void InstructionSelector::VisitFloat64Mod(Node* node) {
}
void InstructionSelector::VisitFloat64Max(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitFloat64Max(Node* node) {
VisitRRRFloat64(this, node, kPPC_MaxFloat64);
}
void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitFloat64Min(Node* node) {
VisitRRRFloat64(this, node, kPPC_MinFloat64);
}
void InstructionSelector::VisitFloat64Sqrt(Node* node) {
@ -1491,7 +1495,9 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
return MachineOperatorBuilder::kFloat64RoundDown |
return MachineOperatorBuilder::kFloat64Max |
MachineOperatorBuilder::kFloat64Min |
MachineOperatorBuilder::kFloat64RoundDown |
MachineOperatorBuilder::kFloat64RoundTruncate |
MachineOperatorBuilder::kFloat64RoundTiesAway;
// We omit kWord32ShiftIsSafe as s[rl]w use 0x3f as a mask rather than 0x1f.