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[arm64] Fix disassembly of unscaled memory operations

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Unscaled memory operations were missing disassembly output for vector registers,
so add support and rewrite as a macro.

Bug: 
Change-Id: I6f388952dbe5a3b9f8a9b9c46e69ef63dc6655ba
Reviewed-on: https://chromium-review.googlesource.com/576177
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Martyn Capewell <martyn.capewell@arm.com>
Cr-Commit-Position: refs/heads/master@{#46785}
This commit is contained in:
Martyn Capewell 2017-07-19 11:31:37 +01:00 committed by Commit Bot
parent b23b8c088c
commit fb98b0c225
2 changed files with 44 additions and 24 deletions
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57
src/arm64/disasm-arm64.cc
View File

@ -823,38 +823,47 @@ void DisassemblingDecoder::VisitLoadStoreRegisterOffset(Instruction* instr) {
Format(instr, mnemonic, form);
}
#define LOAD_STORE_UNSCALED_LIST(V) \
V(STURB_w, "sturb", "'Wt") \
V(STURH_w, "sturh", "'Wt") \
V(STUR_w, "stur", "'Wt") \
V(STUR_x, "stur", "'Xt") \
V(LDURB_w, "ldurb", "'Wt") \
V(LDURH_w, "ldurh", "'Wt") \
V(LDUR_w, "ldur", "'Wt") \
V(LDUR_x, "ldur", "'Xt") \
V(LDURSB_x, "ldursb", "'Xt") \
V(LDURSH_x, "ldursh", "'Xt") \
V(LDURSW_x, "ldursw", "'Xt") \
V(LDURSB_w, "ldursb", "'Wt") \
V(LDURSH_w, "ldursh", "'Wt") \
V(STUR_b, "stur", "'Bt") \
V(STUR_h, "stur", "'Ht") \
V(STUR_s, "stur", "'St") \
V(STUR_d, "stur", "'Dt") \
V(LDUR_b, "ldur", "'Bt") \
V(LDUR_h, "ldur", "'Ht") \
V(LDUR_s, "ldur", "'St") \
V(LDUR_d, "ldur", "'Dt") \
V(STUR_q, "stur", "'Qt") \
V(LDUR_q, "ldur", "'Qt")
void DisassemblingDecoder::VisitLoadStoreUnscaledOffset(Instruction* instr) {
const char *mnemonic = "unimplemented";
const char *form = "'Wt, ['Xns'ILS]";
const char *form_x = "'Xt, ['Xns'ILS]";
const char *form_s = "'St, ['Xns'ILS]";
const char *form_d = "'Dt, ['Xns'ILS]";
const char* mnemonic = "unimplemented";
const char* form = "(LoadStoreUnscaledOffset)";
switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
case STURB_w: mnemonic = "sturb"; break;
case STURH_w: mnemonic = "sturh"; break;
case STUR_w: mnemonic = "stur"; break;
case STUR_x: mnemonic = "stur"; form = form_x; break;
case STUR_s: mnemonic = "stur"; form = form_s; break;
case STUR_d: mnemonic = "stur"; form = form_d; break;
case LDURB_w: mnemonic = "ldurb"; break;
case LDURH_w: mnemonic = "ldurh"; break;
case LDUR_w: mnemonic = "ldur"; break;
case LDUR_x: mnemonic = "ldur"; form = form_x; break;
case LDUR_s: mnemonic = "ldur"; form = form_s; break;
case LDUR_d: mnemonic = "ldur"; form = form_d; break;
case LDURSB_x: form = form_x; // Fall through.
case LDURSB_w: mnemonic = "ldursb"; break;
case LDURSH_x: form = form_x; // Fall through.
case LDURSH_w: mnemonic = "ldursh"; break;
case LDURSW_x: mnemonic = "ldursw"; form = form_x; break;
default: form = "(LoadStoreUnscaledOffset)";
#define LS_UNSCALEDOFFSET(A, B, C) \
case A: \
mnemonic = B; \
form = C ", ['Xns'ILS]"; \
break;
LOAD_STORE_UNSCALED_LIST(LS_UNSCALEDOFFSET)
#undef LS_UNSCALEDOFFSET
}
Format(instr, mnemonic, form);
}
void DisassemblingDecoder::VisitLoadLiteral(Instruction* instr) {
const char *mnemonic = "ldr";
const char *form = "(LoadLiteral)";

11
test/cctest/test-disasm-arm64.cc
View File

@ -1315,6 +1315,17 @@ TEST_(load_store_unscaled) {
COMPARE(ldrsh(x12, MemOperand(x13, -7)), "ldursh x12, [x13, #-7]");
COMPARE(ldrsw(x14, MemOperand(x15, -8)), "ldursw x14, [x15, #-8]");
COMPARE(ldr(b0, MemOperand(x1, -1)), "ldur b0, [x1, #-1]");
COMPARE(ldr(h2, MemOperand(x3, -1)), "ldur h2, [x3, #-1]");
COMPARE(ldr(s4, MemOperand(x5, 255)), "ldur s4, [x5, #255]");
COMPARE(ldr(d6, MemOperand(x7, -256)), "ldur d6, [x7, #-256]");
COMPARE(ldr(q8, MemOperand(x9, 1)), "ldur q8, [x9, #1]");
COMPARE(str(b16, MemOperand(x17, -1)), "stur b16, [x17, #-1]");
COMPARE(str(h18, MemOperand(x19, -1)), "stur h18, [x19, #-1]");
COMPARE(str(s20, MemOperand(x21, 255)), "stur s20, [x21, #255]");
COMPARE(str(d22, MemOperand(x23, -256)), "stur d22, [x23, #-256]");
COMPARE(str(q24, MemOperand(x25, 1)), "stur q24, [x25, #1]");
CLEANUP();
}