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PPC: [wasm-simd] Implement the S128AndNot operation

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Change-Id: I4f1fe15cc7b45218d2c3a189b4ffafc2ca28bbba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2380114
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#69590}
This commit is contained in:
Milad Farazmand 2020-08-27 15:27:28 +00:00 committed by Commit Bot
parent 7a1580a77d
commit fc21339027
5 changed files with 13 additions and 6 deletions
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6
src/codegen/ppc/constants-ppc.h
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@ -2342,7 +2342,9 @@ using Instr = uint32_t;
/* Vector Average Unsigned Byte */ \
V(vavgub, VAVGUB, 0x10000402) \
/* Vector Average Unsigned Halfword */ \
V(vavguh, VAVGUH, 0x10000442)
V(vavguh, VAVGUH, 0x10000442) \
/* Vector Logical AND with Complement */ \
V(vandc, VANDC, 0x10000444)
#define PPC_VX_OPCODE_C_FORM_LIST(V) \
/* Vector Unpack Low Signed Halfword */ \
@ -2373,8 +2375,6 @@ using Instr = uint32_t;
V(vadduqm, VADDUQM, 0x10000100) \
/* Vector Add Unsigned Word Saturate */ \
V(vadduws, VADDUWS, 0x10000280) \
/* Vector Logical AND with Complement */ \
V(vandc, VANDC, 0x10000444) \
/* Vector Average Signed Byte */ \
V(vavgsb, VAVGSB, 0x10000502) \
/* Vector Average Signed Halfword */ \

6
src/compiler/backend/ppc/code-generator-ppc.cc
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@ -3355,6 +3355,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kPPC_S128AndNot: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(0);
__ vandc(dst, src, i.InputSimd128Register(1));
break;
}
case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break;

1
src/compiler/backend/ppc/instruction-codes-ppc.h
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@ -354,6 +354,7 @@ namespace compiler {
V(PPC_S128Zero) \
V(PPC_S128Not) \
V(PPC_S128Select) \
V(PPC_S128AndNot) \
V(PPC_StoreCompressTagged) \
V(PPC_LoadDecompressTaggedSigned) \
V(PPC_LoadDecompressTaggedPointer) \

1
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
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@ -277,6 +277,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_S128Zero:
case kPPC_S128Not:
case kPPC_S128Select:
case kPPC_S128AndNot:
return kNoOpcodeFlags;
case kPPC_LoadWordS8:

5
src/compiler/backend/ppc/instruction-selector-ppc.cc
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@ -2222,10 +2222,11 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(I8x16RoundingAverageU) \
V(S8x16Swizzle) \
V(S128And) \
V(S128Or) \
V(S128Xor) \
V(S8x16Swizzle)
V(S128AndNot)
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
@ -2400,8 +2401,6 @@ void InstructionSelector::VisitS128Select(Node* node) {
void InstructionSelector::VisitS128Const(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16BitMask(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8BitMask(Node* node) { UNIMPLEMENTED(); }