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PPC [liftoff]: Init simd unary ops

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Change-Id: I154b7d70eb9cbcb2f71db7c88a18b81b3814415d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3904424
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#83333}
This commit is contained in:
Milad Fa 2022-09-19 11:43:22 -04:00 committed by V8 LUCI CQ
parent 0cb7542904
commit fd0d2e79ec
4 changed files with 177 additions and 138 deletions
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61
src/codegen/ppc/macro-assembler-ppc.cc
View File

@ -3765,6 +3765,22 @@ SIMD_SHIFT_LIST(EMIT_SIMD_SHIFT)
#undef EMIT_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, xvabsdp) \
V(F64x2Neg, xvnegdp) \
V(F32x4Abs, xvabssp) \
V(F32x4Neg, xvnegsp) \
V(I64x2Neg, vnegd) \
V(I32x4Neg, vnegw)
#define EMIT_SIMD_UNOP(name, op) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
op(dst, src); \
}
SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
#undef EMIT_SIMD_UNOP
#undef SIMD_UNOP_LIST
void TurboAssembler::LoadSimd128(Simd128Register dst, const MemOperand& mem,
Register scratch) {
GenerateMemoryOperationRR(dst, mem, lxvx);
@ -4141,6 +4157,51 @@ void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
vor(dst, dst, scratch);
}
void TurboAssembler::I64x2Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
constexpr int shift_bits = 63;
xxspltib(scratch, Operand(shift_bits));
vsrad(scratch, src, scratch);
vxor(dst, src, scratch);
vsubudm(dst, dst, scratch);
}
void TurboAssembler::I32x4Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
constexpr int shift_bits = 31;
xxspltib(scratch, Operand(shift_bits));
vsraw(scratch, src, scratch);
vxor(dst, src, scratch);
vsubuwm(dst, dst, scratch);
}
void TurboAssembler::I16x8Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
constexpr int shift_bits = 15;
xxspltib(scratch, Operand(shift_bits));
vsrah(scratch, src, scratch);
vxor(dst, src, scratch);
vsubuhm(dst, dst, scratch);
}
void TurboAssembler::I16x8Neg(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
vspltish(scratch, Operand(1));
vnor(dst, src, src);
vadduhm(dst, scratch, dst);
}
void TurboAssembler::I8x16Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
constexpr int shift_bits = 7;
xxspltib(scratch, Operand(shift_bits));
vsrab(scratch, src, scratch);
vxor(dst, src, scratch);
vsububm(dst, dst, scratch);
}
void TurboAssembler::I8x16Neg(Simd128Register dst, Simd128Register src,
Simd128Register scratch) {
xxspltib(scratch, Operand(1));
vnor(dst, src, src);
vaddubm(dst, scratch, dst);
}
Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3,
Register reg4, Register reg5,
Register reg6) {

26
src/codegen/ppc/macro-assembler-ppc.h
View File

@ -1160,6 +1160,20 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#undef PROTOTYPE_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F32x4Abs) \
V(F32x4Neg) \
V(I64x2Neg) \
V(I32x4Neg)
#define PROTOTYPE_SIMD_UNOP(name) \
void name(Simd128Register dst, Simd128Register src);
SIMD_UNOP_LIST(PROTOTYPE_SIMD_UNOP)
#undef PROTOTYPE_SIMD_UNOP
#undef SIMD_UNOP_LIST
void LoadSimd128(Simd128Register dst, const MemOperand& mem,
Register scratch);
void StoreSimd128(Simd128Register src, const MemOperand& mem,
@ -1245,6 +1259,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Simd128Register scratch);
void I8x16GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
Simd128Register scratch);
void I64x2Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I32x4Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I16x8Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I16x8Neg(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I8x16Abs(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
void I8x16Neg(Simd128Register dst, Simd128Register src,
Simd128Register scratch);
private:
static const int kSmiShift = kSmiTagSize + kSmiShiftSize;

125
src/compiler/backend/ppc/code-generator-ppc.cc
View File

@ -2279,6 +2279,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F32x4Abs) \
V(F32x4Neg) \
V(I64x2Neg) \
V(I32x4Neg)
#define EMIT_SIMD_UNOP(name) \
case kPPC_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0)); \
break; \
}
SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
#undef EMIT_SIMD_UNOP
#undef SIMD_UNOP_LIST
case kPPC_F64x2Splat: {
__ F64x2Splat(i.OutputSimd128Register(), i.InputDoubleRegister(0),
kScratchReg);
@ -2470,6 +2487,36 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1), kScratchSimd128Reg);
break;
}
case kPPC_I64x2Abs: {
__ I64x2Abs(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_I32x4Abs: {
__ I32x4Abs(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_I16x8Abs: {
__ I16x8Abs(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_I16x8Neg: {
__ I16x8Neg(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_I8x16Abs: {
__ I8x16Abs(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_I8x16Neg: {
__ I8x16Neg(i.OutputSimd128Register(), i.InputSimd128Register(0),
kScratchSimd128Reg);
break;
}
case kPPC_S128And: {
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src = i.InputSimd128Register(1);
@ -2520,92 +2567,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vsel(dst, src2, src1, mask);
break;
}
case kPPC_F64x2Abs: {
__ xvabsdp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F64x2Neg: {
__ xvnegdp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F64x2Sqrt: {
__ xvsqrtdp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Abs: {
__ xvabssp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Neg: {
__ xvnegsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Sqrt: {
__ xvsqrtsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2Neg: {
__ vnegd(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I32x4Neg: {
__ vnegw(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2Abs: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 63;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrad(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubudm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I32x4Abs: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 31;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsraw(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubuwm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I16x8Neg: {
Simd128Register dst = i.OutputSimd128Register();
__ vspltish(kScratchSimd128Reg, Operand(1));
__ vnor(dst, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vadduhm(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I16x8Abs: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 15;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrah(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubuhm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I8x16Neg: {
Simd128Register dst = i.OutputSimd128Register();
__ xxspltib(kScratchSimd128Reg, Operand(1));
__ vnor(dst, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vaddubm(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I8x16Abs: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 7;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrab(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsububm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_V128AnyTrue: {
Simd128Register src = i.InputSimd128Register(0);
Register dst = i.OutputRegister();

103
src/wasm/baseline/ppc/liftoff-assembler-ppc.h
View File

@ -1876,6 +1876,24 @@ SIMD_SHIFT_RI_LIST(EMIT_SIMD_SHIFT_RI)
#undef EMIT_SIMD_SHIFT_RI
#undef SIMD_SHIFT_RI_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(i64x2_neg, I64x2Neg, fp, fp, , void) \
V(i32x4_neg, I32x4Neg, fp, fp, , void)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
LiftoffRegister src) { \
op(dst.dtype().toSimd(), src.stype().toSimd()); \
return return_val; \
}
SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
#undef EMIT_SIMD_UNOP
#undef SIMD_UNOP_LIST
void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst,
LiftoffRegister src) {
F64x2Splat(dst.fp().toSimd(), src.fp(), r0);
@ -2010,6 +2028,31 @@ void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst,
imm_lane_idx, kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
LiftoffRegister src) {
I64x2Abs(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
I32x4Abs(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i16x8_abs(LiftoffRegister dst,
LiftoffRegister src) {
I16x8Abs(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst,
LiftoffRegister src) {
I16x8Neg(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i8x16_abs(LiftoffRegister dst,
LiftoffRegister src) {
I8x16Abs(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst,
LiftoffRegister src) {
I8x16Neg(dst.fp().toSimd(), src.fp().toSimd(), kScratchSimd128Reg);
}
void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
// TODO(miladfarca): Make use of UseScratchRegisterScope.
@ -2179,16 +2222,6 @@ void LiftoffAssembler::emit_s128_relaxed_laneselect(LiftoffRegister dst,
bailout(kRelaxedSimd, "emit_s128_relaxed_laneselect");
}
void LiftoffAssembler::emit_f64x2_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f64x2_abs");
}
void LiftoffAssembler::emit_f64x2_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f64x2neg");
}
void LiftoffAssembler::emit_f64x2_sqrt(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f64x2sqrt");
@ -2255,16 +2288,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4");
}
void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4_abs");
}
void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4neg");
}
void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4sqrt");
@ -2316,11 +2339,6 @@ void LiftoffAssembler::emit_f32x4_pmax(LiftoffRegister dst, LiftoffRegister lhs,
bailout(kSimd, "pmax unimplemented");
}
void LiftoffAssembler::emit_i64x2_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i64x2neg");
}
void LiftoffAssembler::emit_i64x2_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_alltrue");
@ -2375,11 +2393,6 @@ void LiftoffAssembler::emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst,
bailout(kSimd, "i64x2_extmul_high_i32x4_u unsupported");
}
void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4neg");
}
void LiftoffAssembler::emit_i32x4_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i32x4_alltrue");
@ -2430,11 +2443,6 @@ void LiftoffAssembler::emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst,
bailout(kSimd, "i32x4_extmul_high_i16x8_u unsupported");
}
void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8neg");
}
void LiftoffAssembler::emit_i16x8_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i16x8_alltrue");
@ -2541,11 +2549,6 @@ void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
bailout(kSimd, "i8x16.popcnt");
}
void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i8x16neg");
}
void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "v8x16_anytrue");
@ -2715,26 +2718,6 @@ void LiftoffAssembler::emit_i16x8_rounding_average_u(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i16x8_rounding_average_u");
}
void LiftoffAssembler::emit_i8x16_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i8x16_abs");
}
void LiftoffAssembler::emit_i16x8_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8_abs");
}
void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4_abs");
}
void LiftoffAssembler::emit_i64x2_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2.abs");
}
void LiftoffAssembler::emit_i8x16_sub_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {