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[wasm-simd] Prototype Relaxed Rounding Q-format Multiplication

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Prototype the instruction on the interpreter, and Arm64. Details of
instruction lowerings on all relevant architectures can be found at:
https://github.com/WebAssembly/relaxed-simd/issues/40

Bug: v8:12284
Change-Id: Id4cb3889d94cf0bb7169ea068efe5ca68cfcbad9
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3636365
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
Cr-Commit-Position: refs/heads/main@{#80475}
This commit is contained in:
Deepti Gandluri 2022-05-10 22:16:14 -07:00 committed by V8 LUCI CQ
parent 94b4391dab
commit fe443a4e1f
16 changed files with 58 additions and 2 deletions
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1
src/compiler/backend/arm64/instruction-selector-arm64.cc
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@ -3542,6 +3542,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Mul, kArm64I16x8Mul) \
V(I16x8UConvertI32x4, kArm64I16x8UConvertI32x4) \
V(I16x8Q15MulRSatS, kArm64I16x8Q15MulRSatS) \
V(I16x8RelaxedQ15MulRS, kArm64I16x8Q15MulRSatS) \
V(I8x16SConvertI16x8, kArm64I8x16SConvertI16x8) \
V(I8x16UConvertI16x8, kArm64I8x16UConvertI16x8) \
V(S128Or, kArm64S128Or) \

8
src/compiler/backend/instruction-selector.cc
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@ -2370,6 +2370,8 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI32x4RelaxedTruncF32x4S(node);
case IrOpcode::kI32x4RelaxedTruncF32x4U:
return MarkAsSimd128(node), VisitI32x4RelaxedTruncF32x4U(node);
case IrOpcode::kI16x8RelaxedQ15MulRS:
return MarkAsSimd128(node), VisitI16x8RelaxedQ15MulRS(node);
default:
FATAL("Unexpected operator #%d:%s @ node #%d", node->opcode(),
node->op()->mnemonic(), node->id());
@ -2822,6 +2824,12 @@ void InstructionSelector::VisitI32x4RelaxedTruncF32x4U(Node* node) {
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64
// && !V8_TARGET_ARCH_RISCV64 && !V8_TARGET_ARM
#if !V8_TARGET_ARCH_ARM64
void InstructionSelector::VisitI16x8RelaxedQ15MulRS(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64 && \
!V8_TARGET_ARCH_RISCV64
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM64

3
src/compiler/machine-operator.cc
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@ -607,7 +607,8 @@ std::ostream& operator<<(std::ostream& os, TruncateKind kind) {
V(I32x4RelaxedTruncF32x4S, Operator::kNoProperties, 1, 0, 1) \
V(I32x4RelaxedTruncF32x4U, Operator::kNoProperties, 1, 0, 1) \
V(I32x4RelaxedTruncF64x2SZero, Operator::kNoProperties, 1, 0, 1) \
V(I32x4RelaxedTruncF64x2UZero, Operator::kNoProperties, 1, 0, 1)
V(I32x4RelaxedTruncF64x2UZero, Operator::kNoProperties, 1, 0, 1) \
V(I16x8RelaxedQ15MulRS, Operator::kCommutative, 2, 0, 1)
// The format is:
// V(Name, properties, value_input_count, control_input_count, output_count)

1
src/compiler/machine-operator.h
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@ -924,6 +924,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I32x4RelaxedTruncF32x4U();
const Operator* I32x4RelaxedTruncF64x2SZero();
const Operator* I32x4RelaxedTruncF64x2UZero();
const Operator* I16x8RelaxedQ15MulRS();
// load [base + index]
const Operator* Load(LoadRepresentation rep);

1
src/compiler/opcodes.h
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@ -991,6 +991,7 @@
V(I32x4RelaxedTruncF32x4U) \
V(I32x4RelaxedTruncF64x2SZero) \
V(I32x4RelaxedTruncF64x2UZero) \
V(I16x8RelaxedQ15MulRS) \
V(I8x16Shuffle) \
V(V128AnyTrue) \
V(I64x2AllTrue) \

3
src/compiler/wasm-compiler.cc
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@ -4519,6 +4519,9 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
case wasm::kExprI16x8Q15MulRSatS:
return graph()->NewNode(mcgraph()->machine()->I16x8Q15MulRSatS(),
inputs[0], inputs[1]);
case wasm::kExprI16x8RelaxedQ15MulRS:
return graph()->NewNode(mcgraph()->machine()->I16x8RelaxedQ15MulRS(),
inputs[0], inputs[1]);
case wasm::kExprI16x8Abs:
return graph()->NewNode(mcgraph()->machine()->I16x8Abs(), inputs[0]);
case wasm::kExprI16x8BitMask:

6
src/wasm/baseline/arm/liftoff-assembler-arm.h
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@ -3453,6 +3453,12 @@ void LiftoffAssembler::emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
liftoff::GetSimd128Register(src2));
}
void LiftoffAssembler::emit_relaxed_i16x8_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
bailout(kSimd, "emit_relaxed_i16x8_q15mulr_s");
}
void LiftoffAssembler::emit_i8x16_shuffle(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs,

6
src/wasm/baseline/arm64/liftoff-assembler-arm64.h
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@ -3125,6 +3125,12 @@ void LiftoffAssembler::emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
Sqrdmulh(dst.fp().V8H(), src1.fp().V8H(), src2.fp().V8H());
}
void LiftoffAssembler::emit_relaxed_i16x8_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
Sqrdmulh(dst.fp().V8H(), src1.fp().V8H(), src2.fp().V8H());
}
void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
Abs(dst.fp().V4S(), src.fp().V4S());

6
src/wasm/baseline/ia32/liftoff-assembler-ia32.h
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@ -3631,6 +3631,12 @@ void LiftoffAssembler::emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
I16x8Q15MulRSatS(dst.fp(), src1.fp(), src2.fp(), liftoff::kScratchDoubleReg);
}
void LiftoffAssembler::emit_relaxed_i16x8_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
bailout(kSimd, "emit_relaxed_i16x8_q15mulr_s");
}
void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
if (dst.fp() == src.fp()) {

3
src/wasm/baseline/liftoff-assembler.h
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@ -1248,6 +1248,9 @@ class LiftoffAssembler : public TurboAssembler {
inline void emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2);
inline void emit_relaxed_i16x8_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2);
inline void emit_i32x4_neg(LiftoffRegister dst, LiftoffRegister src);
inline void emit_i32x4_alltrue(LiftoffRegister dst, LiftoffRegister src);
inline void emit_i32x4_bitmask(LiftoffRegister dst, LiftoffRegister src);

3
src/wasm/baseline/liftoff-compiler.cc
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@ -4067,6 +4067,9 @@ class LiftoffCompiler {
case wasm::kExprI32x4RelaxedLaneSelect:
case wasm::kExprI64x2RelaxedLaneSelect:
return EmitRelaxedLaneSelect();
case wasm::kExprI16x8RelaxedQ15MulRS:
return EmitBinOp<kS128, kS128>(
&LiftoffAssembler::emit_relaxed_i16x8_q15mulr_s);
default:
unsupported(decoder, kSimd, "simd");
}

6
src/wasm/baseline/x64/liftoff-assembler-x64.h
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@ -3205,6 +3205,12 @@ void LiftoffAssembler::emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
I16x8Q15MulRSatS(dst.fp(), src1.fp(), src2.fp(), kScratchDoubleReg);
}
void LiftoffAssembler::emit_relaxed_i16x8_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
bailout(kSimd, "emit_relaxed_i16x8_q15mulr_s");
}
void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
if (dst.fp() == src.fp()) {

1
src/wasm/wasm-opcodes-inl.h
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@ -376,6 +376,7 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_I32x4_OP(RelaxedTruncF32x4U, "relaxed_trunc_f32x4_u");
CASE_I32x4_OP(RelaxedTruncF64x2SZero, "relaxed_trunc_f64x2_s_zero");
CASE_I32x4_OP(RelaxedTruncF64x2UZero, "relaxed_trunc_f64x2_u_zero");
CASE_I16x8_OP(RelaxedQ15MulRS, "relaxed_q15mulr_s")
// Atomic operations.
CASE_OP(AtomicNotify, "atomic.notify")

3
src/wasm/wasm-opcodes.h
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@ -540,7 +540,8 @@ bool V8_EXPORT_PRIVATE IsJSCompatibleSignature(const FunctionSig* sig,
V(F32x4RelaxedMin, 0xfd10d, s_ss) \
V(F32x4RelaxedMax, 0xfd10e, s_ss) \
V(F64x2RelaxedMin, 0xfd10f, s_ss) \
V(F64x2RelaxedMax, 0xfd110, s_ss)
V(F64x2RelaxedMax, 0xfd110, s_ss) \
V(I16x8RelaxedQ15MulRS, 0xfd111, s_ss)
#define FOREACH_SIMD_1_OPERAND_1_PARAM_OPCODE(V) \
V(I8x16ExtractLaneS, 0xfd15, _) \

7
test/cctest/wasm/test-run-wasm-relaxed-simd.cc
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@ -410,6 +410,13 @@ WASM_RELAXED_SIMD_TEST(I8x16RelaxedSwizzle) {
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM64 ||
// V8_TARGET_ARCH_RISCV64
#if V8_TARGET_ARCH_ARM64
WASM_RELAXED_SIMD_TEST(I16x8RelaxedQ15MulRS) {
RunI16x8BinOpTest<int16_t>(execution_tier, kExprI16x8RelaxedQ15MulRS,
SaturateRoundingQMul<int16_t>);
}
#endif // V8_TARGET_ARCH_ARM64
#undef WASM_RELAXED_SIMD_TEST
} // namespace test_run_wasm_relaxed_simd
} // namespace wasm

2
test/common/wasm/wasm-interpreter.cc
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@ -2394,6 +2394,8 @@ class WasmInterpreterInternals {
RoundingAverageUnsigned<uint16_t>(a, b))
BINOP_CASE(I16x8Q15MulRSatS, i16x8, int8, 8,
SaturateRoundingQMul<int16_t>(a, b))
BINOP_CASE(I16x8RelaxedQ15MulRS, i16x8, int8, 8,
SaturateRoundingQMul<int16_t>(a, b))
BINOP_CASE(I8x16Add, i8x16, int16, 16, base::AddWithWraparound(a, b))
BINOP_CASE(I8x16Sub, i8x16, int16, 16, base::SubWithWraparound(a, b))
BINOP_CASE(I8x16MinS, i8x16, int16, 16, a < b ? a : b)